| 01:05.42 | *** join/#openjtag clem (~chatzilla@222.45.5.201) |
| 01:06.07 | clem | Hello,I have a question about JTAG. |
| 01:07.21 | clem | There are 5 pins related to JTAG.TDI,TDO,TMS,TCK,nTRST. |
| 01:08.28 | clem | If I only lead 2 pin out of SOC,it's TDI and TCK,can I use JTAG to write a bootloader into a NandFlash? |
| 01:15.29 | Err | no - at the *very* least you'd need TMS, to change the state of the JTAG bus (enable it, basically), and you probably need the nTRST (reset) line as well |
| 01:16.32 | Err | ...and to know if you were successfully communicating before blindly getting the code to work, you would have to have TDO connected as well :-) |
| 01:21.46 | clem | Thank you,Err.I have a question,in a embeded product,is it possible that no JTAG pins have been lead out of the SOC? |
| 01:23.47 | Err | it's certainly possible (if you're asking about a layout not including JTAG - most ICs have JTAG, for boundary scan if nothing else) |
| 01:33.27 | flyback | some ic's might have jtag combined into a few pins but you would need some kinda decoder circuit |
| 01:33.29 | flyback | if that's the case |
| 01:33.41 | flyback | so basically 5 is the min |
| 01:35.10 | clem | The pins in a SOC like a matrix,right?Some pins in the matrix are connected.right?such as TCK,I have tested it and found it connected to many pins in the SOC. |
| 01:35.13 | Err | many modern processors have a simpler method of loading code/flash for bootstrapping (async or sync serial, for instance), accompanied with a PC-side program that will shove in some code... but those ports aren't usually usable for debugging as well |
| 01:44.19 | clem | TCK is connected to many pins lead by character 'V'.TCK is similar to voltage right? |
| 01:51.53 | Err | no, but it may well have an internal pullup |
| 01:52.11 | Err | you probably shouldn't be probing an unpowered processor for continuity :-) |
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| 14:14.07 | of98 | hi |
| 14:14.25 | of98 | someone alive? |
| 14:21.19 | Spida | no. |
| 14:41.52 | of98 | :D |
| 14:43.18 | of98 | anyone knows why it gaves this err mess on this? |
| 14:43.24 | of98 | > reset |
| 14:43.25 | of98 | JTAG tap: s3c2440.cpu UNEXPECTED: 0x000000ff (mfg: 0x07f, part: 0x0000, ver: 0x0) |
| 14:43.25 | of98 | JTAG tap: s3c2440.cpu expected 1 of 1: 0x0032409d (mfg: 0x04e, part: 0x0324, ver: 0x0) |
| 14:43.25 | of98 | Trying to use configured scan chain anyway... |
| 14:43.25 | of98 | s3c2440.cpu: IR capture error; saw 0x0f not 0x01 |
| 14:43.26 | of98 | error: -100 |
| 14:43.58 | of98 | my openocd.cfg is more than basic |
| 14:44.23 | of98 | it has only sources of interface board and target |
| 14:44.39 | of98 | i'm not sure what i need to add |
| 14:45.19 | of98 | haven't found yet a openocd.cfg file spcific for mini2440 |
| 14:46.46 | of98 | cat openocd.cfg |
| 14:46.46 | of98 | source [find interface/olimex-arm-usb-ocd.cfg] |
| 14:46.46 | of98 | source [find board/mini2440.cfg] |
| 14:46.46 | of98 | source [find target/samsung_s3c2440.cfg] |
| 14:46.46 | of98 | ft2232_latency 10 |
| 14:47.04 | of98 | what i've missed? |
| 14:49.26 | Spida | hm, no clue. |
| 14:49.33 | Spida | try the openocd mailinglist |
| 14:49.45 | Spida | if you don't get an answer here |
| 14:52.32 | of98 | thks |
| 15:19.55 | of98 | seems ok if exclude source [find target/samsung_s3c2440.cfg] |
| 15:20.37 | of98 | > reset halt |
| 15:20.37 | of98 | target state: halted |
| 15:20.37 | of98 | target halted in ARM state due to debug-request, current mode: Supervisor |
| 15:20.37 | of98 | cpsr: 0x400000d3 pc: 0x00000000 |
| 15:20.37 | of98 | MMU: disabled, D-Cache: disabled, I-Cache: disabled |
| 15:21.00 | of98 | finally the light at the end of tunnel...:))) |
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| 20:59.47 | of98 | anyone alive? |
| 21:03.57 | of98 | heck...nobody here? |
| 21:04.53 | of98 | 3th time when i come here and no one say nothing... |
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