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| 18:47.46 | _julian_ | hi |
| 18:48.26 | _julian_ | I am new to openocd and am trying to setup a debug chain to a lpc2103 device. I have a usb jtag adapter from www.embedded-projects.org which is directly connected to a lpc2103 jtag interface |
| 18:49.46 | _julian_ | so I did a config with just two source lines - one for interface openocd-usb.cfg and one for target lpc2103.cfg - then I started openocd. now I get this error output |
| 18:50.01 | _julian_ | http://pastebin.com/d23737cbd |
| 18:50.13 | _julian_ | can anyone guide me what might go wrong here? |
| 18:53.49 | zilog | got power for the board, and enabled jtag? |
| 18:54.29 | zilog | my lpc2138 board also has some jumper that affects the bootloader in some fashion (havent got that far yet) that needs to be in a certain position too |
| 18:59.21 | _julian_ | zilog: yes board is powered up and jtag should be enabled |
| 18:59.33 | _julian_ | DBGSEL jumper is set |
| 18:59.57 | _julian_ | I don't know if the reset is driven correctly by the jtag adapter, maybe that's going wrong!? |
| 18:59.57 | zilog | maybe could try a slower jtag speed |
| 19:00.38 | zilog | I use the lpc2138 board from olimex, could compare with the schematic for that |
| 19:01.27 | _julian_ | I can send you the schematics of the board I try to connect to |
| 19:02.05 | zilog | this is my board: http://www.olimex.com/dev/images/lpc-p2138-sch.gif |
| 19:03.00 | zilog | it seems like I need to go as low as jtag_speed 10 even though I use the arm-usb-tiny adapter |
| 19:03.10 | zilog | my old parallell wiggler adapter doesnt work at any speed at all |
| 19:06.08 | _julian_ | damn can't find my scanned schematics... |
| 19:07.03 | _julian_ | ah, found it: http://www.jusst.de/files/minimars-schema.jpeg |
| 19:07.46 | _julian_ | I made an adapter cable for that 12pin jtag header which just connects all the wires straight to their matches on the adapter. rtck is not connected as my adapter has no rtck |
| 19:08.29 | _julian_ | jtag_speed 10 makes no difference |
| 19:10.01 | zilog | maybe the reset configuration is wrong |
| 19:13.31 | _julian_ | what could I try there? |
| 19:14.59 | zilog | I use this: reset_config trst_and_srst srst_pulls_trst |
| 19:15.22 | zilog | I unfortunately know too little of what it corresponds to in the electronics |
| 19:15.38 | zilog | I use lauterbach at work, and we have a gau that manages the config of that one ;) |
| 19:15.43 | zilog | guy |
| 19:16.40 | _julian_ | that's the config I have set as well |
| 19:17.12 | zilog | can you verify with a multimeter or scope that your reset line is pulled low when it should? |
| 19:17.18 | zilog | or that jtag signals really arrive |
| 19:18.24 | _julian_ | maybe the reset is inverted? - as the lpc requires !rst |
| 19:18.24 | _julian_ | yeah can set up the scope. but not this evening. will you be online tomorrwo morning? |
| 19:19.19 | zilog | will be home around this time, maybe 12 hours earlier |
| 19:19.22 | zilog | 1-2 hours |
| 19:19.44 | zilog | but Im not an expert on this, also trying to get my hello world stuff to work ;) |
| 19:21.28 | _julian_ | heh ok - maybe someone else is online as well tomorrow (c: |
| 19:22.08 | zilog | fortunately I still have a job to attend daytime ;) |
| 19:23.06 | zilog | what kind of jtag adapter are you using? |
| 19:23.24 | zilog | I found my laptop producing too low signal voltage to use the parallell port adapter |
| 19:23.27 | _julian_ | this one: http://www.embedded-projects.net/index.php?page_id=256 |
| 19:23.36 | _julian_ | it's a usb adapter |
| 19:24.34 | zilog | never seen that one, but shouldnt have problems with the voltages at least |
| 19:27.40 | _julian_ | hope so |
| 19:30.20 | zilog | what kind of IDE are you planning to use? |
| 19:30.49 | _julian_ | eclipse |
| 19:31.16 | zilog | same here |
| 19:31.34 | zilog | you know how to have several targets in a makefile, and let eclipse choose which one to make? |
| 19:31.35 | _julian_ | actually I have a complete project for that board already. but as the original board engineer used rowley I used this for flashing the board so far as well (using a rowley adapter), butnow I want to switch over |
| 19:31.47 | zilog | I have RAM and ROM targets, but cant figure out how to only make one of them.. |
| 19:31.54 | _julian_ | isn't this possible in the c++ build configuration? |
| 19:32.06 | _julian_ | let me check |
| 19:32.54 | zilog | probably, just dont know how |
| 19:32.58 | zilog | new to eclipse |
| 19:34.30 | _julian_ | in the project preferences under C/C++ Make Project you can at least set a target for "Build" |
| 19:34.36 | zilog | mm |
| 19:34.46 | zilog | seems like I managed to add "RAM" as a target |
| 19:39.22 | _julian_ | I think there is some more convenient way to do this though |
| 19:39.27 | _julian_ | anyway, I need some sleep now |
| 19:39.29 | _julian_ | thanks for your hints |
| 19:41.14 | zilog | night |
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| 23:45.44 | *** topic/#openjtag is this is the place to discuss bootloaders and JTAG |
