| 02:22.13 | *** join/#openjtag keesj (n=keesj@ip49-193-210-87.adsl2.static.versatel.nl) |
| 03:07.42 | *** join/#openjtag brolin (n=brolin@190.157.13.75) |
| 07:25.23 | *** join/#openjtag pleemans (n=toi@116.54-246-81.adsl-static.isp.belgacom.be) |
| 07:47.44 | *** join/#openjtag roxfan2 (n=dunno@112.163-243-81.adsl-dyn.isp.belgacom.be) |
| 08:35.27 | *** join/#openjtag mwalle (n=mw@services.serverraum.org) |
| 08:35.30 | mwalle | hi |
| 08:40.00 | mwalle | does anybody know how h/w debugging works without being able to halt the cpu? do you need special handling in the breakpoint exception? |
| 08:41.49 | mwalle | (i have an lm32 softcpu inside an fpga, but the lm32 core is from lattice and i'm using it with xilinx and trying to create a new target for openocd, but doesn't understand how the h/w debug should work) |
| 08:42.58 | mwalle | i have only jtag commands for reset, break, write control status register, read/write memory and single stepping |
| 08:43.20 | mwalle | and the cpu cant be halted |
| 08:44.19 | mwalle | i cant even read or write registers |
| 08:45.20 | mwalle | so basically there have to be a special exception handler, that writes the registers into memory |
| 10:29.25 | keesj | no sorry |
| 12:35.16 | *** join/#openjtag pirho (i=pirho@gateway/gpg-tor/key-0x2CEEC9CB) |
| 14:09.43 | *** join/#openjtag sesters (n=sesters@76-191-131-184.dsl.static.sonic.net) |
| 14:51.03 | *** join/#openjtag pirho_ (i=pirho@gateway/gpg-tor/key-0x2CEEC9CB) |
| 15:26.14 | *** part/#openjtag sesters (n=sesters@76-191-131-184.dsl.static.sonic.net) |
| 16:04.15 | *** join/#openjtag pirho (i=pirho@gateway/gpg-tor/key-0x2CEEC9CB) |
| 16:51.21 | *** join/#openjtag dirk2 (n=dirk@p5B040A86.dip0.t-ipconnect.de) |
| 19:04.12 | *** join/#openjtag pleemans (n=toi@d54C2AAB7.access.telenet.be) |
| 22:22.17 | *** join/#openjtag brolin (n=brolin@200.24.16.55) |
| 23:51.13 | *** join/#openjtag L_Deluxe (n=lou@c-68-53-134-58.hsd1.tn.comcast.net) |