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| 09:12.43 | *** topic/#openjtag is this is the place to discuss bootloaders and JTAG |
| 12:43.30 | *** join/#openjtag Chocobo (n=swinchen@strongbad.eece.maine.edu) |
| 13:21.28 | *** join/#openjtag prpplague (n=dave@mail.americanmicrosystems.com) |
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| 18:40.01 | *** join/#openjtag drath (n=vmaster@p5B07CA42.dip.t-dialin.net) |
| 18:40.40 | prpplague | drath: greetings |
| 18:40.46 | drath | hey prpplague |
| 18:41.07 | prpplague | drath: any chance you had time to write up a wish list the next gen flyswatter board? |
| 18:41.22 | prpplague | drath: oh and any thoughts on the JRC support in openocd? |
| 18:42.52 | drath | prpplague: iirc you mentioned bit-banging the jtag signals - that feels a bit like wasted (computing) power to me |
| 18:43.09 | drath | prpplague: other than that, i guess an arm9 design that natively runs the openocd would be great |
| 18:44.00 | prpplague | drath: i'm not aware of any other jtag controllers other than the one that is available on the ft2232 |
| 18:44.28 | prpplague | drath: besides, doing bitbang interface isn't too bad, the linux kernel supports bigbanging both i2c and spi directly |
| 18:44.44 | prpplague | drath: without significant impact on performance |
| 18:45.51 | drath | prpplague: have you done any measurements on the possible tck frequency? you'll need two writes and one read per cycle |
| 18:46.11 | drath | prpplague: the arm9s i've seen can do only few mhz |
| 18:46.15 | drath | prpplague: on their gpios |
| 18:46.50 | prpplague | drath: initial test shows i can get around 10MHz |
| 18:47.50 | drath | prpplague: oh, if the s3c24xx is that fast it shouldn't be much of a problem |
| 18:48.17 | prpplague | drath: the other possibility is to use the spi controller and just trick it into doing jtag |
| 18:49.20 | drath | prpplague: either that, if it's flexible enough (some spis are pretty stupid...), or a small cpld for example |
| 18:50.31 | prpplague | drath: any other features other than just having a network connection? |
| 18:51.58 | prpplague | actually, bjdooks whats the best bitbang time you've been able to achieve on something like a 2440 ? |
| 18:52.06 | prpplague | s/2440/2410 |
| 18:52.44 | drath | prpplague: a good analog part, with flexible voltage shifting, and some gpios left to implement support for things that go beyond plain jtag |
| 18:53.26 | prpplague | drath: a good analog part? |
| 18:55.59 | drath | prpplague: level shifting at ~10mhz wont be too easy |
| 18:56.42 | prpplague | drath: yea, the ti part we have is pretty solid |
| 18:56.52 | prpplague | drath: we are still testing some stuff |
| 18:57.19 | prpplague | drath: what do you think the minimal tclk freq would be for a midrange device? |
| 18:57.24 | prpplague | 5MHz? |
| 18:59.57 | drath | the ftdi equals sustained 1.5-2mhz - twice as good is definitely a minimum |
| 19:00.34 | prpplague | drath: i'll setup some more tests with the scope to see what we get |
| 19:03.13 | drath | regarding the JRC stuff - if this is going to become common among newer uC designs, i would like to see a clean implementation that allows the jtag chain to be adjusted during runtime |
| 19:04.26 | prpplague | drath: yea, from what i can tell, this the way most manufacturers are going when more than one device is involved, such as arm+dsp |