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| 14:15.08 | gandhijee | i dunno, i'm trying to use it to program the flash memory of my IXP 465 with a wiggler |
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| 15:16.41 | sn9 | gandhijee: make sure the cpu is halted |
| 15:17.22 | gandhijee | i get scan errors |
| 15:17.45 | gandhijee | i'll set it back up in a lil bit, i got the code for the wiggler software for windows |
| 15:18.02 | gandhijee | but i'd rather get openOCD running |
| 15:19.02 | sn9 | you'll get scan errors if the reset protocol is wrong |
| 16:05.42 | gandhijee | well all of the settings give me erros |
| 16:10.40 | gandhijee | this is the error i get |
| 16:10.41 | gandhijee | http://pastebin.ca/964825 |
| 16:12.49 | sn9 | if the scan always returns zero, the jtag simply isn't connected |
| 16:14.52 | gandhijee | i c |
| 16:17.53 | sn9 | some devices make you jump through some hoops to enable it |
| 16:18.09 | gandhijee | how so? |
| 16:20.19 | sn9 | various ways |
| 16:21.01 | sn9 | but, if your windows software works, it must just be some kind of setting |
| 16:21.04 | gandhijee | you know anything for IXP4xx devices? |
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| 20:05.57 | ali_as | Hi all, whats the state of the art with the fastest open design for a jtag interface, USB/FTDI or better? |
| 20:28.17 | prpplague | ali_as: ft2232 seems to be item of choice, we use it for the flyswatter and have yet to have a problem with performance or reliability |
| 20:28.51 | ali_as | Limited to less than about 5Mbit though? |
| 20:29.04 | prpplague | that sounds about right |
| 20:29.14 | prpplague | ali_as: jtag wasn't really designed for high speed |
| 20:30.58 | ali_as | Some parts go to 80MHz. My lpt port dabblings are rather slow. A few K a second for ejtag. |
| 20:31.44 | prpplague | indeed |
| 20:32.04 | ali_as | I asked about geep-b in #openhardware and it was suggested that project died. |
| 20:32.23 | prpplague | ali_as: the ft2232 is fast enough for us to flash nor/nand as well as debug and do co-verification |
| 20:32.34 | prpplague | ali_as: no real complaints for us |
| 20:32.41 | prpplague | us==me and my employeer |
| 20:34.23 | ali_as | I like the idea of an ethernet solution, so I'm dabbling in this directionwith a development board. |
| 20:35.03 | prpplague | ali_as: it is doable |
| 20:36.02 | ali_as | I've hit limitations of bus speed with the oki arm chip, so I'm hunting round for how other people are solving the problem. |
| 20:36.44 | prpplague | might try one of our hammer boards |
| 20:36.57 | prpplague | http://www.elinux.org/Hammer_Board |
| 20:38.27 | ali_as | Ok, thats a confusing spec, 200MHz ARM9 delivering 100MIPS. |
| 20:39.01 | sn9 | haha |
| 20:39.02 | prpplague | ali_as: thats an incorrect posting, that should be 100BogoMIPS |
| 20:39.15 | prpplague | ali_as: its 220MIPS |
| 20:40.57 | bjdooks | ali_as: BogoMIPS are 'Bogus' MIPS and are barely reliable between the same CPU cores |
| 20:41.15 | ali_as | That sounds right. Surprised and pleased the ARM9 cores are reaching strongarm speeds. |
| 20:41.27 | prpplague | ali_as: that too is incorrect |
| 20:41.32 | ali_as | I take it the peripheral bus is dog slow though? |
| 20:41.40 | bjdooks | much better memory bus, and StrongARM where generally 200 |
| 20:41.53 | prpplague | ali_as: you are comparing clock speeds when you also have to consider the number of stages of pipes for the device |
| 20:41.54 | bjdooks | whereas most ARM9s can reach 266 or even 533MHz |
| 20:42.55 | ali_as | From memory strongarm had more stages and the barrel shifter was bypassed when not used. |
| 20:43.19 | prpplague | ali_as: more stages than an arm9 |
| 20:43.22 | prpplague | sorry |
| 20:43.24 | prpplague | arm7 |
| 20:43.36 | bjdooks | the shifter is basically free on pretty much all arm cores |
| 20:44.13 | prpplague | ali_as: arm9 and strongarm basically have the same 5 stages |
| 20:44.42 | prpplague | ali_as: xscale has an odd 7/8 stage, whereas true arm11 has 8 |
| 20:45.23 | ali_as | I havn't looked at the ARM9 recently, I went for the ARM7 board by simtec as it has a 10/100 Ethernet chip and cpld. |
| 20:46.00 | ali_as | But it only runs at 60MHz and the bus itself can barely push 15Mhz. |
| 20:47.06 | ali_as | I understand the peripheral bus is very very slow on the ARM chips generally, so bitbanging the gpio's is too slow to be useful. |
| 20:47.58 | bjdooks | ali_as: the internal busses on the ARM9 devices is generally run at 66MHz |
| 20:48.20 | ali_as | xscale is what strongarm became when intel ate DEC, now sold to marvel I'm told. |
| 20:49.05 | ali_as | Intel is pushing x86 for mobile embedded applications now but they can't yet match ARMs MIPS/Watt advantage. |
| 20:49.10 | sn9 | i thought compaq ate dec |
| 20:49.45 | bjdooks | hmm, i'm not sure if compaq ate all of dec |
| 20:49.55 | ali_as | They certainly aquired the alpha, and then killed it. |
| 20:50.00 | sn9 | yes |
| 20:50.14 | ali_as | I think a fab and rights to strongarm went to intel. |
| 20:50.33 | sn9 | yes, but when it was still dec |
| 20:51.10 | ali_as | bjdooks, busses plural, including the 'B' bus? |
| 20:51.29 | bjdooks | On our S3C2440, the AHB runs 133, APB at 66 |
| 20:51.52 | ali_as | Thats damn good. |
| 20:52.13 | ali_as | I stand corrected. |
| 20:52.20 | bjdooks | The AHB goes to a few blocks, and an AHB<>APB bridge |
| 20:52.48 | bjdooks | where most of the slower peripherals such as UARTs and suchlike live |
| 20:53.03 | ali_as | And the GPIO's usually. |
| 20:55.54 | prpplague | bjdooks: thats the same as ours |
| 20:56.26 | prpplague | bjdooks: wait no thats incorrect, we run our AHB at 100 since we are using lowpower sdram |
| 20:56.34 | prpplague | bjdooks: our 2410 is at 133 |
| 21:00.37 | ali_as | simtec are running their ram at about 1Mhz. I have the feeling they wern't really trying. |
| 21:03.38 | bjdooks | ? |
| 21:03.38 | ali_as | Is the hammer board full speed usb only? |
| 21:04.20 | prpplague | ali_as: correct |
| 21:04.25 | ali_as | Its an ARM7 board, almost all the default settings in the supplied uclinux build have timings at the slowest they can possibly be. |
| 21:04.50 | ali_as | uclinux build/bootloader. |
| 21:04.54 | bjdooks | I know the IO settings are conservative, but the SDRAM should be running at full speed |
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| 21:05.54 | ali_as | I'm a little out of love with simtec, submitted a query and the website says it will be answered within "28 days". |
| 21:06.14 | ali_as | This is day 23. |
| 21:06.44 | prpplague | points to bjdooks |
| 21:07.53 | ali_as | Good grief, that name was ringing a very tiny bell in the back of my head, you work for simtec Ben? |
| 21:08.13 | bjdooks | yes |
| 21:08.53 | ali_as | Then I apologise partially for the rant :) |
| 21:10.15 | bjdooks | I don't have access to the support system, so can't fish out the query |
| 21:10.49 | ali_as | Thats fine, I figured out the answer after three days, I'm leaving the query in there now just to see how long it takes. |
| 21:11.51 | bjdooks | <PROTECTED> |
| 21:11.55 | bjdooks | bah |
| 21:12.44 | ali_as | I rather expected that to be worst case, in the middle of a hurricane sort of time. |
| 21:13.51 | ali_as | The headaches I'm getting currently arn't from the board itself, but from the oki chip anyway. |
| 21:15.55 | ali_as | I will pick your brain if I may though. Any idea how fast the timings on the ethernet chip can be run reliably? |
| 21:18.40 | ali_as | The register is currently set to 4 for bank0/1, which is 2 =12 =6 clock cycles. |
| 21:18.57 | ali_as | Whoops, 2+12+6 clocks. |
| 21:20.54 | gandhijee | does anyone know if i can use the Keil ULINK with openOCD? |
| 21:22.58 | ali_as | (On the OKI 675001DIP). |
| 21:34.18 | bjdooks | ali_as: I'm not sure if it can go lots faster, it does require a bit of recovery time after access |
| 21:35.09 | ali_as | I'll check the datasheet again, I thought it would operate at 15 or 20Mhz. |
| 21:35.37 | bjdooks | the access times can be fast, it just needs delays between the address and data registers |
| 21:35.49 | ali_as | Ahhh. |
| 21:38.45 | ali_as | I'm implimenting a latch in the cpld and getting 135ns between STRH's after turning the bus to 1+1+1. I was after a jtag device throughput of 1M/sec, with the ethernet chip at 2+12+6 I was starting to doubt that was even possible. |
| 21:40.12 | bjdooks | ali_as: if it is just gpio, i think the gpio block would be faster |
| 21:40.26 | bjdooks | ali_as: otherwise, implement a shift-register in the cpld |
| 21:41.25 | ali_as | A much more complicated cpld design is on the cards. |
| 21:41.41 | bjdooks | personal or work? |
| 21:41.53 | ali_as | Personal. |
| 21:42.26 | bjdooks | yeah, I started something like that and then got distracted by shiny FPGAs |
| 21:43.08 | ali_as | I'm the other way around, I was burned by xilinx fpgas and see cplds as a much safer option. |
| 21:43.22 | bjdooks | I tend to get burned by soldering irons |
| 21:44.14 | ali_as | When I implimented ejtag on a wiggler I ended up with a data rate around 3K/second. |
| 21:44.39 | bjdooks | the modern pcs at work can get close to 1MHz |
| 21:44.53 | ali_as | Which is not funny if you want to transfer 64M. |
| 21:44.53 | bjdooks | but PCs with parallel ports are a dying breed, so we moved to FTDI |
| 21:45.42 | ali_as | I use an lpt port card, so my effective tck is not much under 1MHz. |
| 21:46.59 | ali_as | EJTAG was not designed to be a high speed protocol, it's one of the ones you have to spoon feed the cpu instructions in order to get data in or out. |
| 21:47.17 | bjdooks | yeah, using the DCC helps a lot |
| 21:47.33 | ali_as | DCC? |
| 21:47.43 | bjdooks | sending data using the DCC block in the ICE |
| 21:47.51 | bjdooks | 32bit comms register |
| 21:48.15 | bjdooks | OpenOCD uses it for the 'fast' download modes |
| 21:49.06 | ali_as | If this is DMA mode then it died somewhere around EJTAG 2.5. |
| 21:49.31 | bjdooks | i've not tried EJTAG |
| 21:50.29 | ali_as | Ahh. EJTAG is evolving backwards. 2.0 had a DMA mode, 2.5 you have to stall the cpu and feed it instructions. |
| 21:50.57 | bjdooks | ah, i'm generally using OpenOCD with the ARMs we ave |
| 21:51.45 | prpplague | we use 8 ft2232 devices on one device to do gang testing/programming of our arm cpu boards |
| 21:53.09 | ali_as | At the moment I'm interested in a solution that will work with ARM/MIPS/ST20/ST40 and a few others. |
| 21:53.17 | prpplague | we do a series of tests on a few of the critical gpio's, some sdram and flash tests, and them flash the board |
| 21:53.49 | ali_as | OpenOCD is heading is some very nice directions. |
| 21:54.29 | ali_as | I have read that Athlon chips have a jtag interface and can be debugged thhrough it. |
| 21:54.50 | prpplague | bjdooks: you guys use jtag to do any hardware verification? or just for flashing and debugging? |
| 21:54.53 | bjdooks | wonders if he is going to regret buying another Gigabyte board |
| 21:55.24 | bjdooks | prpplague: some basic, then a full test suite is run which is also available to the user to try |
| 21:55.28 | ali_as | prp, using boundary scan? |
| 21:55.35 | prpplague | ali_as: yea |
| 21:57.31 | ali_as | I've dabbled with that in my own programs, something I want to work on. |
| 21:57.50 | ali_as | Are you using tools developed inside the company for those tasks? |
| 21:58.07 | prpplague | ali_as: openocd |
| 21:58.47 | ali_as | I didn't know it could do that. I only found out about the project recently. |
| 21:59.26 | prpplague | ali_as: it is not design to do hardware verification, but it can be tweaked and use openocd scripts to do the job |
| 21:59.52 | prpplague | ali_as: we use the gpio lines of the ft2232 to verify different lines as well as upload test programs and execute them |
| 21:59.58 | gandhijee | can openOCD be used to flash memory? |
| 22:00.08 | prpplague | gandhijee: hehe yea |
| 22:00.08 | ali_as | Running bit algorithms to test the board tracks, that sort of thing? |
| 22:00.14 | prpplague | yea |
| 22:11.50 | ali_as | I am starting to question my need for high clock rates. My current pet mips cpu is limited to 5MHz TCK anyway. |
| 22:12.29 | ali_as | But ethernet still solves so many problems I can't do easily by usb. |
| 22:46.52 | bjdooks | goes to finish building his new AMD Phenom based machine |
| 22:49.40 | ali_as | Why AMD out of interest? |
| 22:50.21 | ali_as | I'm about to upgrade and for the first time I'm planning to defect to intel. |
| 22:50.58 | ali_as | Oh 'goes' misread. |
| 22:53.16 | bjdooks | got an Phenom 9500 after all the hassle with this gigabyte/nvidia board, ended up buying a gigabyte/amd-fx570 instead |
| 22:54.54 | ali_as | My old athlon has an msi motherboard, lpt port is glitchy like nothing on earth. Months of trying to track down faults in my circuits that wern't there. |
| 22:55.20 | bjdooks | i'm setting it up as a build/test box then possibly swapping my desktop out to become my media pc... got my eye on a nice silverstone technology HTPC case |
| 22:55.49 | ali_as | I'm with you on the media pc idea. I want my next one to be watercooled and completely silent. |
| 22:56.33 | bjdooks | i'm just looking at some decent coolers for an AMD x2 system |
| 22:56.57 | ali_as | The 45nm core2 chips look really good though, so I'm splitting with amd. |
| 22:58.34 | bjdooks | http://www.bjorn3d.com/read.php?cID=857 |
| 23:00.02 | ali_as | Six hard drive spaces! |
| 23:01.51 | ali_as | Geforce graphics cards problems, I'm wondering if that means the 8800's won't fit. |
| 23:06.22 | bjdooks | i'm not even sure if i'll bother with one, and just boot the os over the network |
| 23:17.16 | ali_as | It's a stunning case but I'd hate to find out I didn't have enough space for a decent graphics card. Mine needs to be a complete replacement and I don't have a server. |
| 23:30.45 | ali_as | I've looked through the dm9000 manual and I can't see any requirements for extra delays. The raw cpu interface could almost be run at 1+1+1. |
| 23:31.30 | ali_as | But at 20ns write strobe its under the 22ns spec. |
| 23:35.28 | bjdooks | is that the dm9000a, dm9000b or dm9000e |
| 23:37.02 | ali_as | That's a good question. |
| 23:37.46 | ali_as | The manual just says dm9000, I assumed it applied to any and all in the range. |
| 23:38.34 | ali_as | It's an E on the board. |
| 23:39.43 | ali_as | Ahh, the order info in this data sheet is for the E only, so it matches. |
| 23:40.33 | bjdooks | the A and B parts are newer and faster |
| 23:41.03 | ali_as | Yeah, this is from 2004, but if this is worst case I don't see where the problem is. |
| 23:42.23 | bjdooks | you are welcome to try. you could always use ncs2/ncs3 to talk to the cpld |
| 23:42.50 | ali_as | Currently I am doing, aparently that loses me nWait delays. |
| 23:44.18 | ali_as | I've taken bank 2/3 down to 1+1+1 and the cpld works fine, but if I can't get data to the ethernet fast enough it would be a waste working out a complicated cpld jtag design. |
| 23:45.45 | ali_as | I'm after one megabyte a second, on the basis my micro connect lists around $3000 and does one megabit. |