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| 09:51.37 | Griffon26 | guys, I'm looking for some documentation on how a program on the target can receive data through JTAG. Do you maybe have some links for me? |
| 09:52.43 | vmaster | could you specify /the target/ a bit more? |
| 09:55.18 | Griffon26 | well, at this point I don't even understand how JTAG can be used to communicate between host and target (no matter what kinds). I've always thought JTAG has a very limited set of instructions that can do things like write memory. |
| 09:55.43 | Griffon26 | I mean communication between running processes |
| 09:56.03 | Griffon26 | in some way faster than the standard way of accessing memory |
| 09:56.15 | vmaster | mhh, okay: |
| 09:56.32 | vmaster | jtag specifies a statemachine, a set of registers, and 4 pins that allow serial access to these registers |
| 09:56.46 | vmaster | there's an instruction register, that allows you to select one of several instructions |
| 09:56.56 | vmaster | depending on the current instruction, a data register is selected |
| 09:57.07 | vmaster | the size of these shift-registers is defined by the application |
| 09:57.22 | vmaster | JTAG itself further defines boundary-scanning using these shift registers |
| 09:57.39 | vmaster | there are up to three bits in the boundary scan register for each device pin |
| 09:58.08 | vmaster | the EXTEST instruction for example allows you to read the inputs from the device pins, and drive certain outputs |
| 09:58.23 | vmaster | the INTEST instruction does the same, but toward the "inside" of the chip |
| 09:58.51 | vmaster | everything beyond that, like accessing memory on a certain microcontroller, isn't part of the JTAG specs |
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| 10:07.16 | Griffon26 | so, if I get this correctly, the way to communicate with a running process on the target with standard JTAG is to set some GPIO pins with boundary scan and have the process read them |
| 10:08.25 | vmaster | uhm, yeah, but then you'd have to implement everything in software |
| 10:10.18 | vmaster | the ARM7 and ARM9 for example has a built-in JTAG interface. It has two major JTAG data registers, one that accesses the data/instruction bus, and one that accesses a few special debug registers (EmbeddedICE) |
| 10:10.24 | Griffon26 | The thing is, I have this JTAG probe working with my MIPS, but it's really slow in downloading. Now I heard about faster ways of transferring data and they apparently involved downloading a small program and running it on the target, and then have that program receive more data over JTAG. Unfortunately I don't have any details. |
| 10:11.16 | vmaster | okay, you'll have to consult the mips datasheets - this totally depends on the MIPS |
| 10:12.32 | Griffon26 | so what is the fastest way to transfer data to a platform with an ARM? Does it involve downloading and running a small application first? |
| 10:13.01 | vmaster | yes |
| 10:13.20 | vmaster | the ARM's have a "Debug Communications Channel (DCC)" |
| 10:13.30 | vmaster | it's a 32-bit register, that can be written with little overhead |
| 10:13.47 | Griffon26 | interesting |
| 10:13.51 | vmaster | but it requires software running on the target to read that register, and to write the data to the target memory location |
| 10:14.20 | vmaster | so basically you set up the target with the base address, number of words to transfer, and a small algorithm that polls the DCC register, and writes whatever it gets to memory |
| 10:15.23 | vmaster | what are you currently using? the openwince jtag tools? |
| 10:15.49 | Griffon26 | no, we bought an Ashling probe |
| 10:16.21 | Griffon26 | I'm using their GDB server |
| 10:17.50 | vmaster | what speeds do you achieve? |
| 10:18.11 | vmaster | and are you talking about writing to RAM or to Flash? |
| 10:18.56 | Griffon26 | I haven't measured it, but I can go get coffee if I'm downloading a linux kernel (couple of MB) |
| 10:19.06 | Griffon26 | to RAM |
| 10:19.28 | Griffon26 | eventually we'll want to write everything through JTAG, flash and PROMs |
| 10:21.33 | Griffon26 | can't find much info about DCC though |
| 10:24.01 | vmaster | the DCC is something specific to the EmbeddedICE Unit of ARM7 and ARM9 (and ARM10 iirc) |
| 10:24.27 | vmaster | i'm just browsing the EJTAG specs |
| 10:24.41 | vmaster | it really seems to be a rather slow way of implementing debugging |
| 10:25.54 | Griffon26 | yeah, except for DMA |
| 10:26.01 | Griffon26 | but that's not in later MIPSes =( |
| 10:26.15 | Griffon26 | or was it later EJTAG.. I forget |
| 10:27.05 | vmaster | "MIPS EJTAG has two modes, one is "DMA" mode where the JTAG can cause CPU bus cycles directly, the other "PrAcc" is where the JTAG interface is used to respond to CPU memory accesses in a special range of memory (DMSEG, 0xFF200000)" |
| 10:28.15 | vmaster | "EJTAG version 2.0 in their chips. This allows the use of DMA transfers via JTAG which, while slow, is faster than the implementation of EJTAG v2.5 and v2.6 which do not support DMA transfers." |
| 10:29.20 | Griffon26 | exactly |
| 10:29.28 | Griffon26 | guess which one we have |
| 10:30.02 | vmaster | hehehe |
| 10:30.15 | vmaster | ok, PrAcc is a nice "idea", but it is almost bound to be slow |
| 10:31.08 | Griffon26 | especially if you have a probe on USB1.x |
| 10:32.06 | Griffon26 | btw, is there a USB2.0 FT2232 by now? |
| 10:32.24 | vmaster | haven't heard of one |
| 10:32.43 | vmaster | FTDI seems to have issues with 2.0 stuff |
| 10:33.18 | Griffon26 | "ft2232d: USB 2.0 Full Speed" hmm |
| 10:35.56 | Griffon26 | oh wait.. there was some internal limitation |
| 10:37.10 | Griffon26 | grmph.. nm me. I always mix up full speed and hi-speed |
| 10:39.18 | vmaster | heh, yeah, i have that problem, too |
| 10:39.22 | vmaster | full-speed sounds so promising |
| 10:44.11 | Griffon26 | yeah, I mean, there's always higher, but full is just full |
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