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12:36.17 | *** join/#openjtag vmaster (n=vmaster@p549B6289.dip.t-dialin.net) |
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12:48.36 | zumbi | hello! |
12:49.25 | vmaster | zumbi: hi |
12:49.33 | zumbi | :-) |
12:50.36 | zumbi | i'm planning to add daisy chain jtag to a circuit with many FPGAs -i'm new to daisy chain- so... |
12:51.42 | zumbi | ... jtag is for programming purposes. The question i have is if you know if i have to do daisy chaining with eeproms or FPGAs, and if you know some example schematic |
12:53.30 | vmaster | daisy chaining is rather easy - just connect TDI->TDO from one device to the next, and connect TCK and TMS (optionally TRST) to each device in parallel |
12:54.04 | vmaster | you might run into problems with too many devices in the chain though |
12:54.18 | zumbi | vmaster: but memories (EEPROM)? (there are 3 devices) |
12:54.58 | vmaster | is there a jtag port on these eeproms? |
12:55.32 | zumbi | vmaster: i guess, it's an eeprom for that FPGA |
12:56.18 | vmaster | Xilinx? |
12:56.59 | zumbi | yes |
12:57.24 | zumbi | http://direct.xilinx.com/bvdocs/publications/ds123.pdf |
12:57.37 | zumbi | those are programming memories |
12:58.19 | zumbi | anyway, vmaster, thank you very much |
13:00.44 | zumbi | vmaster: about openjtag, how is the project status ? do you need some volunteer help? |
13:02.17 | vmaster | i don't think there's a lot happening here lately. someone started working on a ARM9+FPGA board (iirc) to allow high JTAG speeds, but haven't heard about this project for a while |
13:04.05 | vmaster | regarding your fpgas: if you have JTAG available at each FPGA, you can configure them on the fly, without writing the EEPROM each time |
13:04.58 | vmaster | the datasheet mentions problems with some devices that follow the standard close enough - some change TDO on the rising edge of TCK, and some on the falling edge |
13:05.44 | vmaster | s/that follow/that don't follow/ |
13:06.14 | zumbi | i see |
13:07.19 | zumbi | well, thanks |
13:07.51 | [g2] | vmaster I think things are warming up a little |
13:08.35 | vmaster | [g2]: yeah, i saw AchiestDragon online, but I believe this is only temporary? |
13:10.02 | [g2] | vmaster I'm talking about something else |
13:10.14 | vmaster | [g2]: ah, ok :) |
13:14.29 | [g2] | vmaster what kinda of jtag speeds do you see with the Olimex usb jtag device ? |
13:15.13 | vmaster | the FT2232 achieves about 1.5-2 MHz effective JTAG clock while debugging an ARM7/9 |
13:15.35 | vmaster | that's good enough for downloading at ~120kb/s |
13:15.49 | [g2] | that's pretty fast |
13:16.07 | vmaster | fast enough for most purpose, imho |
13:16.15 | vmaster | s/purpose/purposes/ |
13:16.39 | [g2] | yeah fast enough that it's not painful |
13:25.16 | zumbi | have you used opencores' usb core for these purposes? |
13:35.32 | wookey_ | some of the balloon people have developed a fast jtag widget too: |
13:35.34 | wookey_ | http://balloonboard.org/~lwithers/urppd/ |
13:35.55 | wookey_ | using cypress EZ-USB device |
13:36.06 | wookey_ | released under GPL2 |
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15:45.25 | *** join/#openjtag prpplague (n=dave@mailhost.amltd.com) |
17:25.27 | prpplague | vmaster: http://pastebin.ca/196499 |
17:36.27 | vmaster | hey prpplague |
17:37.21 | vmaster | could you run again with debugging enabled (-d) |
17:37.22 | vmaster | ? |
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17:55.15 | prpplague | vmaster: you turn on the highdrive for your ft2232 based devices? |
17:56.17 | vmaster | only for the one that doesn |
17:56.20 | vmaster | 't have buffers |
17:56.24 | prpplague | hmm |
17:56.38 | prpplague | i'm having alot of problems with one of prototype boards |
17:57.12 | prpplague | vmaster: its communicates but get a ton of errors |
17:57.22 | vmaster | did you try lowering the speed? |
17:57.25 | prpplague | vmaster: yea |
17:57.30 | prpplague | vmaster: all the way down to 10 |
17:58.51 | vmaster | you removed R9/C9 on that board, too? |
17:59.08 | prpplague | yea |
18:00.01 | prpplague | vmaster: whats interesting is that my board worked fine with the leds, but these act like the leds are drawing too much current |
18:00.26 | prpplague | vmaster: i've removed the leds for now, but it still seems like something isn't right |
18:00.52 | prpplague | i'm wondering if dlpdesign changed their default firmware settings |
18:01.18 | prpplague | vmaster: did you use the linux example code to turn on the high driver outputs? |
18:01.34 | vmaster | yeah, the windoze stuff never worked for me |
18:02.13 | prpplague | vmaster: i have a very hard time with ftdi docs, do i simply set the value in the eeprom to 0x01 to enable high drive? |
18:02.48 | vmaster | the eeprom stuff is barely documented, iirc |
18:03.28 | vmaster | <PROTECTED> |
18:03.46 | vmaster | that's what I changed in sample/EEPROM/write/main.c |
18:06.02 | prpplague | vmaster: ok gotcha |
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18:07.33 | prpplague | vmaster: hmm, you have to write all the values back out? |
18:08.03 | prpplague | vmaster: hmm, what is the max current you have on your devices? |
18:15.23 | prpplague | vmaster: don't suppose you could give me a eeprom dump of one of your working devices? |
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18:21.32 | vmaster | prpplague: sorry, just had a doner kebap for lunch |
18:22.07 | vmaster | prpplague: i'll send you a dump and the .c file i've used to program it |
18:22.31 | prpplague | vmaster: thanks |
18:27.20 | vmaster | prpplague: mmd.ath.cx/ft2232_highdrive.c |
18:27.42 | vmaster | dumping the eeprom is only possible with libftdi, right? |
18:28.08 | prpplague | vmaster: seems to be possible with the d2xx |
18:28.25 | prpplague | vmaster: under samples there is a read function |
18:42.50 | vmaster | http://mmd.ath.cx/ft2232_highdrive.c |
18:44.43 | vmaster | http://mmd.ath.cx/EEPROM.dump |
18:45.02 | vmaster | the output from read/main.c is ASCII, if you'd like, I could modify it so it dumps to a file |
19:14.36 | prpplague | vmaster: thanks |
19:14.48 | prpplague | vmaster: think we found the problem with one of the jtag lines on the main board |
19:14.54 | prpplague | vmaster: its very noisy |
19:34.21 | vmaster | prpplague: could you figure out why? |
19:35.10 | prpplague | vmaster: looks to be a board layout issue |
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