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| 13:22.36 | prpplague | vmaster: morning |
| 13:23.40 | vmaster | hey prpplague |
| 13:24.10 | prpplague | vmaster: you said you used your dlpdesign module without any buffers correct? |
| 13:25.17 | vmaster | yeah |
| 13:25.47 | vmaster | just a 3v3 regulator from the 5v usb, but vref would probably have been an even better choice |
| 13:35.11 | prpplague | vmaster: yea, just let the voltage from the target board provide the voltage |
| 13:35.29 | prpplague | vmaster: you got a schematic done up? |
| 14:06.27 | vmaster | it's the one in my thesis, on the openocd page (openocd.berlios.de/web/) |
| 14:06.31 | vmaster | USBJTAG-1 |
| 14:10.29 | prpplague | vmaster: ok thanks |
| 14:14.43 | prpplague | vmaster: you said you had to make some changes to the eprom config using that schematic? |
| 14:25.14 | vmaster | yeah, the default is to drive with something like 5ma, but you can enable a high-drive mode with 10 or 15ma |
| 14:26.07 | prpplague | vmaster: ahh ok |
| 14:28.50 | prpplague | vmaster: not gonna hurt to try it with the current settings? |
| 14:38.54 | vmaster | no, not at all |
| 16:30.40 | prpplague | vmaster: ping |
| 16:39.03 | vmaster | prpplague: pong |
| 16:40.32 | prpplague | vmaster: on the m5960 schematic |
| 16:40.48 | prpplague | vmaster: i removed r9 and 9 |
| 16:40.52 | prpplague | and c9 |
| 16:41.00 | prpplague | vmaster: works with no errors now |
| 16:41.08 | prpplague | vmaster: getting about 50kbps |
| 16:41.25 | vmaster | to flash? that's probably as good as it gets with the ft2232 |
| 16:42.01 | prpplague | yea |
| 16:42.13 | vmaster | mhh, what were r9 and c9 supposed to do? |
| 16:42.21 | prpplague | vmaster: jtag_speed set to 1 seems the best |
| 16:42.44 | prpplague | vmaster: i spoke to our ee, according to him it was for use with flexible cables, per ieee standards |
| 16:43.12 | prpplague | vmaster: but after showing him several other schematics we decided that was cause the tdo to bleed off incorrectly |
| 16:43.29 | vmaster | heh, guess you should tell your cable to read the ieee standards then |
| 16:43.35 | prpplague | yea |
| 16:44.00 | prpplague | doing some speed tests now |
| 16:44.15 | prpplague | vmaster: so i can start openocd with a script and exit correct? |
| 16:44.20 | vmaster | yeah |
| 16:44.39 | prpplague | lovely |
| 16:45.02 | prpplague | vmaster: ever tried running multi copies of openocd on one pc? |
| 16:45.03 | vmaster | target_script <target#> <event_name> <script_file> binds a script to a particular event |
| 16:45.17 | vmaster | prpplague: yeah, it works, but the USB controller might become a bottleneck |
| 16:45.31 | vmaster | latency is critical, not sure how multiple devices are going to behave |
| 16:45.37 | prpplague | vmaster: yea, we got a pc with 4 seperate controllers |
| 16:45.43 | vmaster | ah, ok |
| 16:46.02 | vmaster | currently, the only event is "reset", which would better be called "init" |
| 16:46.21 | vmaster | it's delivered after the target entered debug state in case of "reset_init" or "run_and_init" |
| 16:46.56 | vmaster | if the s3c behaves good in reset (most arm9 do), you can use "reset_init" to halt the target right at the reset vector |
| 16:47.03 | vmaster | and execute the script |
| 16:47.13 | prpplague | vmaster: yea, seems so |
| 16:47.14 | vmaster | as the last command in the script issue a shutdown |
| 16:47.31 | vmaster | wait_halt allows you to pause script execution until debug was actually reached |
| 16:49.04 | prpplague | ahh cool deal |
| 16:49.06 | prpplague | thats perfect |
| 16:49.39 | prpplague | vmaster: we'll be able to do some basic tests, then flash the unit and we'll be done |
| 16:49.55 | vmaster | yep |
| 16:50.13 | prpplague | run a full speed test now |
| 16:50.24 | vmaster | well, there's no error handling in the script support so far |
| 16:50.25 | prpplague | the flash erase doesn't seem any faster, but the flash process does |
| 16:50.42 | vmaster | flash erase time is mostly dictated by the device |
| 16:50.47 | prpplague | yea |
| 16:50.51 | vmaster | i.e. the openocd is polling faster than the device erases anyway |
| 16:51.28 | prpplague | my guess is that it will take 90 seconds to do 4mb |
| 16:51.41 | prpplague | 94 seconds |
| 16:52.14 | prpplague | vmaster: the dcc downloads process, that do any type of error checking? |
| 16:52.26 | vmaster | none at all |
| 16:52.31 | prpplague | hmm |
| 16:52.34 | vmaster | it just pretends that the target is always faster than the jtag |
| 16:53.50 | vmaster | a verify stage would be easy to implement - reading is >50kbyte/s |
| 16:55.12 | prpplague | yea, thats what i was thinking |
| 16:55.46 | prpplague | 72 seconds for 16mb flash erase, 94 seconds flash programming, 10 misc |
| 16:56.29 | vmaster | ah, the cfi code is not endianess safe yet - you'll definitely run into problems with big endian targets or hosts |
| 16:56.44 | vmaster | it's not a lot that's required, but i've had no time yet, and nothing to test with anyway |
| 16:56.54 | vmaster | everything else should work with either endianness |
| 16:57.37 | prpplague | vmaster: yea, we are little endian |
| 17:09.48 | prpplague | vmaster: i do seem to get some verification errors with fast_memory_access |
| 17:12.43 | vmaster | i'd have to do some calculations, but maybe 12mhz and 3mhz jtag clock are too close |
| 17:12.58 | vmaster | you could try enabling the pll |
| 17:13.17 | vmaster | that should be scriptable, too |
| 17:14.44 | prpplague | vmaster: yea i'm running with the pll enabled |
| 17:15.16 | prpplague | vmaster: i'm not see that big of a difference with the fast memory access anyway |
| 17:33.55 | vmaster | yeah, it's only used to upload the DCC code anyway |
| 17:34.13 | vmaster | and chunks of less than 128 byte, which is a rare when doing flash writes |
| 17:36.00 | prpplague | well, looks good |
| 17:36.05 | prpplague | vmaster: thanks for the help |
| 17:36.17 | prpplague | vmaster: we will be making this available soon along with the schematic |
| 17:36.29 | prpplague | vmaster: we have a line of small dev boards coming out as well |
| 17:36.59 | prpplague | vmaster: hhoegl's web page seems defunct |
| 17:37.20 | prpplague | vmaster: i made a pdf of just the usbjtag-1 schematic from your thesis |
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| 18:23.27 | prpplague | muasch|swiss12: d00d |
| 18:23.34 | prpplague | muasch|swiss12: whats the story? |
| 18:23.44 | prpplague | there are three of you now? |
| 18:24.07 | muasch|swiss12 | prpplague, sorry. i have some problems with one of my wlan-routers :( |
| 18:24.32 | prpplague | muasch|swiss12: ok just wanted to make sure it wasn't some sort of bot trying to do a take-over |
| 18:25.04 | muasch|swiss12 | ah no. i'will disconnect from irc the next time i play with my router ;-) |
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| 19:26.35 | rwhitby | vmaster: ping |
| 19:28.08 | vmaster | rwhitby: pong |
| 19:36.28 | rwhitby | vmaster: we have a guy at work who is now modifying openocd to support the processor arch we discussed previously |
| 19:36.44 | rwhitby | Will you have some time this week to review our changes to make sure we're on the right track? |
| 19:37.11 | rwhitby | (We expect, lawyers willing, that the changes will be contributed back to openocd) |
| 19:38.34 | rwhitby | The lawyers should be fine, cause they should be able to understand our GPL commitments (quite apart from our true desire to contribute back, but lawyers never understand that) |
| 19:42.25 | vmaster | rwhitby: yeah, sure |
| 19:42.58 | vmaster | rwhitby: if questions from his side arise i'm here to answer |
| 19:45.24 | rwhitby | vmaster: thx |
| 19:45.34 | rwhitby | will talk on Monday |
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