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| 06:03.47 | *** join/#openjtag AchiestDragon (n=dave@whipy.demon.co.uk) |
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| 11:39.18 | Griffon26 | anyone ever figure out how EJTAG's FASTDATA works? I've read the spec, but I can't make heads or tails of it. |
| 12:03.38 | vmaster | heh, i find the whole concept of the MIPS EJTAG rather confusing |
| 12:09.38 | AchiestDragon | not as confusing as doing user loadable microcode instruction macros theres actual a big preformance problem when you are running a opperating system and the cpu is emulating a ppc for one app and a x86 for another , not to mention that the os is writen in its native assembly |
| 12:11.10 | AchiestDragon | thats it takes longer for the cpu to swap the microcode sets when switching task that you may as well use 3 cpus |
| 12:16.21 | AchiestDragon | is there a dat sheet for it ,, a link ? |
| 12:20.19 | vmaster | http://www.mips.com/content/Documentation/MIPSDocumentation/EJTAG/doclibrary |
| 12:22.00 | AchiestDragon | :( got to register to view anything there |
| 12:22.39 | vmaster | http://www.amslink.com/file/mipsart1.html |
| 12:22.47 | vmaster | this is a nice (and short) explanation |
| 12:23.00 | AchiestDragon | kool ty |
| 12:26.04 | AchiestDragon | k so whats confusing you about it |
| 12:27.25 | vmaster | heh, well, i only had a brief look, and the idea of having the core explicitly request debug-handler operations from the EJTAG probe seems a bit confusing |
| 12:29.21 | AchiestDragon | no ,, like a mode bit ,, if you initalise it with the jtag and put it in debug mode , they can easaly add extra debug checking bits to the instruction sequence |
| 12:30.56 | AchiestDragon | they have a predefined set of them that will control things like break point and conditional debug instructions also |
| 12:31.31 | AchiestDragon | can be done with little extra logic on the silicone |
| 12:33.02 | AchiestDragon | but mips desing there own cores so they have the choice of how they impliment it , but the concept is fine |
| 12:35.18 | AchiestDragon | its quite a good way for high tolarance systems that would use say 3 or 4 of thease doing the same job and using the jtag to compare the results |
| 12:36.45 | AchiestDragon | and not only that but if one gives the wrong result it beeing able to pinpoint the error and fix it or work arround it |
| 12:39.50 | AchiestDragon | it looks like it takes quite a lot of i/o pads to allow for it 25 by the looks of it |
| 12:40.54 | AchiestDragon | but bet its in a bga package so wont realy matter that mutch |
| 12:45.01 | AchiestDragon | you could probablay do remote code exicution via the jtag on it , but it would take a long time , could be usefull for getting around a boot flash fail , or loading a boot loader to program the flash |
| 12:47.14 | AchiestDragon | that gives it production advantages , like it just gets plugged into one machine and it runs the boundry scan , initalises the flash and runs a self test and returns the result ,, |
| 12:52.22 | AchiestDragon | think that is the sort of thing that should be posible even on microcontrolers |
| 12:53.45 | AchiestDragon | there a sod to debug in the same way , you end up trying to simulate it than actualy beeing able to see any real data |
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