| 00:13.20 | *** join/#openjtag ka6sox (n=ka6sox@nslu2-linux/ka6sox) |
| 03:01.40 | [g2] | ka6sox cool |
| 06:16.48 | *** join/#openjtag DaKa (n=david@193.13.58.211) |
| 13:18.58 | *** join/#openjtag prpplague (n=billybob@72.22.128.49) |
| 14:43.41 | *** join/#openjtag vmaster_ (i=vmaster@p549B79AD.dip.t-dialin.net) |
| 15:08.58 | *** join/#openjtag dwery (n=dwery@nslu2-linux/dwery) |
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| 18:39.49 | ka6sox-office | do you have a Crystal Ball? |
| 18:40.01 | AchiestDragon | lol |
| 18:46.24 | *** join/#openjtag dwery (n=dwery@nslu2-linux/dwery) |
| 18:48.05 | ka6sox-office | prpplague stands by a microwave oven and yells "Hurry!!!!" |
| 18:49.04 | vmaster | yesterday he didn't show up before 22:00 my time - that's two more hours |
| 18:49.24 | ka6sox-office | it *is* early here on the Left Coast |
| 18:50.32 | prpplague | hehe he just sent out a flurry of emails |
| 18:52.06 | lennert | ka6sox-office: i got the dual espresso hooked up |
| 18:52.23 | lennert | ka6sox-office: now only to get 2.6 running |
| 18:52.42 | lennert | double espresso, even -- sheesh |
| 19:05.40 | ka6sox-office | yum! |
| 19:05.48 | ka6sox-office | give me a Double Bartender! |
| 19:06.07 | lennert | :D |
| 19:14.26 | *** join/#openjtag bullet (n=bullet@1.23.79.83.cust.bluewin.ch) |
| 19:18.34 | lennert | there's something wrong with the pci-x to pci-e bridge though |
| 19:33.12 | ka6sox | bummer |
| 19:34.04 | lennert | well, it's misprogrammed -- i'll sort it out, i guess |
| 20:29.39 | AchiestDragon | hmmm , ok so the max jtag rate posible for a ppc runing at 2.2Ghz is 137.5 mhz according to ibm for the ppc970fx , think the i/o on the fpga will handle that no problems |
| 20:35.37 | AchiestDragon | and ram bandwith is not going to be a problem at that rate , as a burst mode clock rate of 12mhz for ram access would give us a bit rate of 192mhz max jtag so its down to what the fpga will be able to drive the thing to |
| 20:38.36 | AchiestDragon | given that the ram has a burst rate that clocks upto 100 mhz then 1.6ghz jtag bit rate would be the max that is theoreticaly posable so the limit is down to the i/o on the fpga and the bufers |
| 20:50.30 | AchiestDragon | ok looks like 142mhz is the limit of the fpga inputs |
| 20:50.47 | ka6sox-office | the internal FPGA is only capable of 260MHZ |
| 20:51.04 | ka6sox-office | so that will part of the limiting factor...BIG long shift registers. |
| 20:51.33 | AchiestDragon | yes |
| 20:52.01 | AchiestDragon | back on couple of hrs |
| 20:52.23 | ka6sox-office | as a practical limit we can expect 240mhz out of our chip with the 40mhz clock |
| 20:54.36 | vmaster | heh, i wouldn't know what to do with 100mhz jtag clock... maybe write every byte twice, just because we can ;) |
| 20:55.01 | ka6sox-office | think debugging and it becomes important |
| 20:55.45 | vmaster | all i'm thinking is debugging |
| 20:57.30 | vmaster | 100mhz would give 7mb/s download speed |
| 20:58.22 | vmaster | how many i/o lines does the logic analyzer have? |
| 21:00.27 | AchiestDragon | 16 + 1 clock but thats limited to the 100mhz ram bandwidth |
| 21:00.59 | vmaster | it would make a nice platform for the embeddedtrace unit available on many arms |
| 21:16.48 | *** join/#openjtag ByronT (n=byron-po@nslu2-linux/ByronT) |
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| 23:12.44 | AchiestDragon | yes , seem to remeber seeing one when i was looking for diferent jtag pinouts , but think that used more inputs |