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| 01:23.55 | *** join/#openjtag vmaster_ (i=vmaster@p549B6950.dip.t-dialin.net) |
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| 03:49.11 | *** mode/#openjtag [+o ChanServ] by irc.freenode.net |
| 03:52.07 | ka6sox | ~seen Chanserv |
| 03:52.15 | purl | ka6sox: i haven't seen 'chanserv' |
| 03:52.24 | lennert | chanserv sig11d.. wow |
| 03:52.53 | ka6sox | ~seen ChanServ |
| 03:52.54 | purl | ka6sox: i haven't seen 'chanserv' |
| 03:52.59 | ka6sox | heh |
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| 04:54.10 | ka6sox | morning velinp |
| 04:54.30 | velinp | ka6sox: morning |
| 04:55.43 | velinp | ka6sox: PM about debian-armeb ? |
| 04:58.22 | ka6sox | didn't see one |
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| 18:20.12 | vmaster | hmm... someone familiar with sdram setup here? |
| 19:27.19 | AchiestDragon | vmaster: in what way |
| 19:27.36 | AchiestDragon | timings or interface |
| 19:43.23 | AchiestDragon | http://www.micron.com/products/dram/sdram/technote.html < theres lots of related applications notes here for sdrams |
| 19:58.00 | AchiestDragon | http://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf < for timings and info needed for interfacing one |
| 22:48.58 | vmaster | AchiestDragon: i'm facing a very strange problem: when writing some addresses, two locations change, for example when writing 0x41feaa00, 0x41feaa40 changes, too |
| 22:49.15 | vmaster | but it's only 0x40 and 0x00 |
| 22:49.22 | lennert | odd.. |
| 22:49.41 | vmaster | and only one some addresses, i.e. not every 0x40 is aliased to 0x00 |
| 22:50.14 | vmaster | s/one/on/ |
| 22:58.15 | vmaster | my problem is that i'm not sure if a faulty sdram setup could cause a problem like that, or if i should look for other possible mistakes |
| 23:00.33 | [g2] | vmaster new board ? |
| 23:00.52 | [g2] | or new sdram ? |
| 23:01.18 | [g2] | sometimes a line get shorted and the connection is transient |
| 23:01.50 | vmaster | mhh, old board, and known to work with a different bootloader |
| 23:02.07 | vmaster | but that bootloader is ugly, so i wanted to move to u-boot |
| 23:02.29 | [g2] | ahh |
| 23:02.36 | [g2] | CS timing ? |
| 23:04.54 | vmaster | all the sdram controller registers are set to the same values... is the sdram mode register something standardised? |
| 23:06.11 | [g2] | there's nothing else on the address bus (like a CPLD or anything is there) ? |
| 23:08.41 | [g2] | vmaster the there idea is that maybe the sdram controller regs are the same, but maybe the clock is from a different reference |
| 23:08.59 | [g2] | causing the actual bus timings to be different |
| 23:09.31 | [g2] | or the VM setup with the MMU |
| 23:09.40 | vmaster | i'm just looking at this... the original bootloader selects 64mhz, while the u-boot port defaults to 70mhz (the chip should handle these) |
| 23:10.08 | [g2] | can you select the 64 ? |
| 23:10.17 | vmaster | yeah, it |
| 23:10.23 | vmaster | 's just a different value in the pll reg |
| 23:10.40 | [g2] | nod |
| 23:10.50 | [g2] | That's what I'd try |
| 23:11.01 | [g2] | just as a timing test |
| 23:11.24 | [g2] | maybe the picked 64 for a reason :) |
| 23:12.17 | [g2] | were's AchiestDragon's logic analyzer when you need it! |
| 23:13.27 | vmaster | ohh... please... looks like it's working at 64mhz - i got the u-boot prompt |
| 23:13.54 | [g2] | cool |
| 23:14.44 | [g2] | this is the kind of thing I was talking about reading out the chip's state |
| 23:14.52 | AchiestDragon | http://www.whipy.demon.co.uk/aztag1b.zip < close |
| 23:15.02 | [g2] | he |
| 23:15.03 | [g2] | heh |
| 23:15.48 | [g2] | AchiestDragon want to talk over the ISA bus right on the PC104 correct ? |
| 23:16.04 | [g2] | s/want/you wan/t |
| 23:16.14 | [g2] | s/want/you want/ |
| 23:16.25 | [g2] | AchiestDragon you want to talk over the ISA bus right on the PC104 correct ? |
| 23:36.13 | vmaster | [g2]: thanks. that stupid clock seems to be the problem |
| 23:40.58 | [g2] | vmaster np |
| 23:41.15 | [g2] | I didn't do anything |
| 23:44.18 | AchiestDragon | g2 yes |
| 23:47.21 | AchiestDragon | tidying up the schematics atm and the silk screens for the pcb , just needs verifying and checking atm |
| 23:51.45 | [g2] | AchiestDragon are you building pcb's and going to get them stuffed ? |
| 23:52.54 | AchiestDragon | so schedual atm is to allow a month for verification of the design , if ok and no faults or errors spotted or changes then should be ordering the first batch of 5 pcbs at end of feb |
| 23:54.17 | *** part/#openjtag sinclair73de (n=sinclair@p54A0A051.dip0.t-ipconnect.de) |
| 23:54.21 | AchiestDragon | still to do on that pcb space is the adaptor boards , so although seperate will still be in a 160*100mm pbc aria |
| 23:56.19 | AchiestDragon | could of done those on seperate artwork but as one of each adaptor will be required with each main pcb then may as well have them panalized together |
| 23:58.39 | [g2] | what tool to see the .gxx files ? |
| 23:58.48 | AchiestDragon | gerber files |
| 23:59.06 | [g2] | yeah Is there a tool you normally use :) |
| 23:59.12 | AchiestDragon | GTL and GBL are the top and bottom pcb layers |
| 23:59.33 | AchiestDragon | ? for linux , but there are ones arround , |
| 23:59.52 | AchiestDragon | i use the one in dxp that will also view them |