| 00:00.58 | AchiestDragon | k , by changing his design slightly fitting 8 bit dual voltage buffers rather than 4 it is posible to use the same circut for both the jtag and logic analizer functions , but would require a non std cable to the adaptors |
| 00:01.39 | ka6sox-office | ah...we should discuss this with him next time he comes onboard. |
| 00:02.54 | AchiestDragon | k |
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| 01:17.15 | key2 | ka6sox-office: what's ep1220's board ? |
| 01:19.35 | *** join/#openjtag vmaster_ (i=vmaster@p549B603A.dip.t-dialin.net) |
| 01:20.04 | ka6sox-office | a universal interface (voltage/connector) for JTAG. |
| 01:20.34 | key2 | ka6sox-office: url ? |
| 01:20.47 | ka6sox-office | there isn't one yet. |
| 01:20.52 | ka6sox-office | its an Alpha board. |
| 01:21.06 | key2 | what is it based on? |
| 01:21.48 | key2 | fpga ? |
| 01:24.37 | ka6sox-office | FT2232 currently |
| 01:24.50 | key2 | it's slow |
| 01:25.05 | key2 | i tryed jtag with it |
| 01:25.15 | key2 | honestly, u can't really do anything with it |
| 01:25.30 | key2 | it's almost as slow as parallal |
| 01:25.42 | key2 | since the latency of the USB port is high |
| 01:25.44 | ka6sox-office | which is why all the discussion about how to make it faster using other methods. |
| 01:25.54 | key2 | well |
| 01:25.57 | key2 | then I have an idea |
| 01:26.11 | key2 | that would be quiet good but lil more expensive |
| 01:26.46 | key2 | ka6sox-office: you take a little FPGA and put all the JTAG operation in it (read/write/readwrite...) |
| 01:27.13 | ka6sox-office | thats what we are discussing |
| 01:27.24 | key2 | you stick a little arm7 to it |
| 01:27.27 | key2 | well |
| 01:27.28 | key2 | i've done it |
| 01:27.41 | key2 | i tryed first doing it with a scenix |
| 01:27.45 | key2 | that can bitbang quiet fast |
| 01:28.00 | key2 | but it's a 8bit microcontroller so it's not fast enough for handling everything |
| 01:28.14 | key2 | i think the best idea is this one |
| 01:28.22 | key2 | fpga + arm + ft2232 |
| 01:28.46 | key2 | one part of the ft2232 would be used for reprogramming the ARM the other part for communicating with it |
| 01:29.35 | key2 | so basically you could for example if you have a MIPS, use a special binary u made with GCC to burn into the ARM, then you have your protocol with the ARM via USB but the other part of the 2232 |
| 01:30.11 | key2 | you use it as a parallel for communicating with the ARM and the serial part of the 2232 for reprogramming the arm7 |
| 01:30.50 | key2 | and then if you need to adjust the voltage of the JTAG, you use a simple double buffer.. |
| 01:31.12 | key2 | it would cost at the end about 40euros each PCB included |
| 01:31.26 | ka6sox-office | there is a lot more to it since some targets provide voltage and some don't |
| 01:31.41 | ka6sox-office | some targets use a 6 pin connector and some use a 20 pin connector. |
| 01:31.45 | key2 | you can use a switch |
| 01:31.55 | ka6sox-office | thats one way. |
| 01:32.00 | key2 | well 20 pins for having just 4 of them really used ? |
| 01:32.11 | ka6sox-office | yes that is sometimes true. |
| 01:32.19 | ka6sox-office | but its what we need to talk to. |
| 01:32.27 | ka6sox-office | its not for just one platform. |
| 01:32.34 | key2 | well then you can eventually reprogramm the ucf of the fpga |
| 01:32.53 | ka6sox-office | that is a PITA |
| 01:32.54 | key2 | and put a standard 20 pins ribbon connector |
| 01:32.58 | key2 | PITA ? |
| 01:33.17 | ka6sox-office | what we plan on doing is putting the StD connector and adapters |
| 01:33.29 | ka6sox-office | that will allow us to work universally |
| 01:33.39 | ka6sox-office | Pain In The ARse. |
| 01:34.12 | key2 | ASS |
| 01:34.13 | key2 | ok |
| 01:34.14 | key2 | got it |
| 01:34.32 | key2 | ka6sox-office: but the board has to be something we would sell ? |
| 01:34.42 | key2 | or it would be something that the user has to make himself ? |
| 01:34.59 | ka6sox-office | either way |
| 01:35.10 | ka6sox-office | I'm up for whatever makes it go. |
| 01:35.12 | key2 | well |
| 01:35.15 | AchiestDragon | just debating if to use the high dencity ribbon cable like used on ata133 ide drives , that may give us a 80Mhz jtag clock rate |
| 01:36.50 | key2 | it's nto that easy to get a single FPGA |
| 01:36.50 | key2 | how fast has to be the clock rate ? |
| 01:36.51 | ka6sox-office | most of the FPGA's I have will clock internally to 260mhz and externally at least 1/2 of that. |
| 01:36.51 | key2 | PPL ? |
| 01:37.15 | ka6sox-office | PPL? |
| 01:38.41 | key2 | well basically you have an external clock of 50mhz and with the PLL u get it up to 100 if you multiply by 2 |
| 01:38.43 | key2 | oh |
| 01:38.44 | key2 | sorry |
| 01:38.44 | key2 | PLL |
| 01:38.45 | key2 | .. |
| 01:40.32 | ka6sox-office | the reference in our case is 40mhz and I'll PLL it up to 240mhz. |
| 01:40.57 | key2 | what kind of xilinx would you use |
| 01:41.05 | key2 | what would be big enough just for a state machine |
| 01:41.19 | key2 | so we can put all the JTAG function in it |
| 01:41.40 | AchiestDragon | a xc3s400-4tq144c |
| 01:41.53 | key2 | bga? |
| 01:42.03 | AchiestDragon | 144pin tqfp |
| 01:42.20 | key2 | oh k |
| 01:42.22 | ka6sox-office | NO BGA... |
| 01:42.28 | ka6sox-office | not possible to fix. |
| 01:42.44 | key2 | what is it ? |
| 01:42.48 | key2 | spartan 2 ? 3 ? |
| 01:42.52 | ka6sox-office | 2 |
| 01:42.54 | ka6sox-office | er 3 |
| 01:43.28 | key2 | sounds good |
| 01:43.35 | AchiestDragon | and bga would need a 4 or more layer pcb , its a dubble sided pcb if it routes ok , and thats looking good atm |
| 01:44.50 | key2 | so one of those plus one ARM so anyone could programm it with a GCC for it's own stuff plus a bft2232 for reprogramming the ARM and communicating with and some bullshit for adjusing the voltage would be fine right ? |
| 01:45.35 | key2 | and we could bitbang up to 100Mhz easy |
| 01:46.20 | AchiestDragon | with the pc104 vesion we should not need the bdi2232 unit , that woulde be a lower speed alternative |
| 01:46.57 | key2 | 10Mhz |
| 01:47.00 | key2 | that's quiet slow |
| 01:47.20 | key2 | plus you need sometimes to do a lot of calculation between each bit |
| 01:47.23 | key2 | dunno if it's great |
| 01:47.43 | key2 | oh |
| 01:47.45 | key2 | sorry |
| 01:47.53 | AchiestDragon | what at 10mhz |
| 01:47.54 | AchiestDragon | ? |
| 01:48.05 | key2 | well without the ft2232 you won't be able to communicate fast |
| 01:48.22 | key2 | or we're not talkin about the same pc104 |
| 01:49.08 | AchiestDragon | we got 32mb / 64mb of sdram attached to the fpga |
| 01:49.45 | key2 | what for ? |
| 01:49.58 | key2 | not sure you need that much for JTAG |
| 01:49.59 | key2 | .. |
| 01:50.27 | key2 | it's not a mem issue it's more a bitbanging issue |
| 01:50.31 | AchiestDragon | maybe not , but its cheaper than sram and that size is cheep |
| 01:50.54 | key2 | gimme url of the pc104 |
| 01:51.29 | AchiestDragon | 16 bit wide , so the max bit bang rate is going to be 16 times the read / write cycle time of the ram |
| 01:52.05 | key2 | AchiestDragon: what PC104 u talkin about ? |
| 01:52.41 | ka6sox-office | key2, the RAM is helpful for doing captures and standalone operation. |
| 01:52.43 | AchiestDragon | the fpga board im working on at for this |
| 01:52.55 | AchiestDragon | at = atm |
| 01:55.39 | ka6sox-office | the S3/RAM combo will give us a lot of flexibility |
| 01:56.14 | key2 | but the 32Mbit are not included into the FPGA |
| 01:56.21 | key2 | that's something you wanna put apart |
| 01:56.23 | key2 | rigjht ? |
| 01:56.39 | AchiestDragon | http://www.whipy.demon.co.uk/JTAG.PS < block diagram of the card |
| 01:59.48 | key2 | of what card ? |
| 01:59.56 | key2 | don't have postscript reader |
| 02:00.34 | AchiestDragon | the high speed fpga jtag tester card |
| 02:01.03 | AchiestDragon | <PROTECTED> |
| 02:04.14 | key2 | who made it |
| 02:04.53 | ka6sox-office | we are making it :) |
| 02:17.03 | beewoolie-afk | AchiestDragon: nice picture |
| 02:18.43 | AchiestDragon | ty |
| 05:13.39 | *** join/#openjtag bullet (n=bullet@210.16.78.83.cust.bluewin.ch) |
| 06:00.06 | *** join/#openjtag ka6sox (n=ka6sox@nslu2-linux/ka6sox) |
| 06:04.19 | ka6sox | ~seen Tiersten |
| 06:04.29 | purl | tiersten is currently on #nslu2-linux (11h 42m 22s) #openjtag (11h 42m 22s) #openslug (11h 42m 22s), last said: 'The wiki hasn't been updated lately sorry'. |
| 06:05.33 | ka6sox | Tiersten: when you have time could you please approve the url that beewoolie has on the info:JTAGprotocol page? |
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| 08:39.11 | ka6sox | morning |
| 08:40.48 | lennert | morning |
| 08:41.03 | vmaster | morning |
| 08:42.31 | vmaster | a question regarding achiest's 2-layer design - are 2 layers enough for good signal conditions? |
| 08:49.09 | ka6sox | vmaster, it depends |
| 08:49.21 | ka6sox | if done right it works just fine. |
| 08:49.32 | ka6sox | done poorly its a nightmare. |
| 08:53.35 | ka6sox | I've done boards that operate at 450mhz in 2 sided that have no problems at all. |
| 08:54.02 | vmaster | oh, ok |
| 08:55.28 | ka6sox | I'm confident that we can do this correctly in 2 layer (and save about $40/board) |
| 08:56.11 | ka6sox | the real reason for needing 4layer is if we don't have room for adequate traces for Power and Ground. |
| 09:00.18 | ka6sox | Lennert: when you were poking around in the JTAG chain of the FPGA that you were playing with were you able to just "figure out" what they were doing? |
| 09:03.13 | lennert | ka6sox: the s3? yeah, pretty much. |
| 09:03.55 | ka6sox | did you have bsdl files? |
| 09:04.15 | lennert | yup |
| 09:04.51 | ka6sox | how far off were they? |
| 09:05.22 | lennert | it seemed pretty accurate, as far as idcode, opcodes, DR scan chain and IR format goes |
| 09:05.36 | lennert | i did't check _everything_ but the things i did check were very accurate |
| 09:10.06 | ka6sox | thanks. |
| 09:10.19 | ka6sox | we had a discussion earlier about BSDL files and accuracy. |
| 09:14.36 | lennert | what part of the bsdl file would be inaccurate? |
| 09:15.16 | ka6sox | sometimes bit functions are either not explained or marked "reserved" with no explaination. |
| 09:15.50 | lennert | well, ok, but some things you can't describe in the bsdl file anyway |
| 09:16.01 | ka6sox | true |
| 09:16.08 | lennert | for example, the sp3 bsdl file doesn't explain what the CFG_IN opcode does, you need to look at the application notes for taht |
| 09:17.45 | ka6sox | okay so a little research and we might be able to "discover" thing that we will need for working with the various targets. |
| 09:17.59 | ka6sox | s/thing/things |
| 09:19.20 | ka6sox | time for sleep here...nite all |
| 09:19.50 | lennert | nite |
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| 13:58.14 | AchiestDragon | ka6sox: ka6sox-office ,, ping |
| 14:14.58 | vmaster | my best guess is that he isn't up yet |
| 14:15.09 | AchiestDragon | np |
| 14:15.18 | vmaster | usually ~16:00 your time |
| 14:17.39 | AchiestDragon | k , is working on the high speed jtag board , looks like we could get a bit faster speed if we use .5" pitch ribbon cable between the board and the adaptor plug |
| 14:19.12 | AchiestDragon | the cheapest option would be a 40pin (80way cable) like the ata133 ide drives use , but that is a 2" wide cable so not realy a practical option |
| 14:19.45 | vmaster | are there lvds ports available on the s3? |
| 14:21.12 | *** join/#openjtag GyrosGeier (n=richter@p5499786A.dip.t-dialin.net) |
| 14:21.48 | AchiestDragon | grr , did not save the data sheet , 1 min |
| 14:23.10 | vmaster | as i understand it, lvds seems to be a common answer to the problems that arise when having to go from one board to another at higher speeds |
| 14:32.06 | AchiestDragon | the fpga will do GTL,HSTL,LVCMOS,LVTTL,PCI,SSTL and diferential modes LDT,LVDS,LVPECL,RSDS,HSTL and SSTL |
| 14:32.08 | AchiestDragon | but |
| 14:34.01 | AchiestDragon | that is direct from the fpga and its buffered with a auto sencing level conveter so we will just use one standard from the fpga , and the buffers will convert the levels for us |
| 14:38.28 | AchiestDragon | theres more than that reason for using buffers also , in that if you blow up an input its easyer and cheaper to change a 24 pin buffer than a 144pin fpga |
| 14:40.38 | AchiestDragon | ie when you acidentaly mistake a 10 pin rs232c header for a 10 pin jtag port and get +and -12v up the interface |
| 14:46.36 | vmaster | okay, the arm realview ice offers either a normal connection, or a lvds connection that uses an additional small board that plugs directly into the standard 20-pin arm header - and the faq states that this probe is necessary at speeds >=20mhz |
| 14:47.03 | vmaster | so the buffer converting between lvds and target voltage sits on the probe-pcb |
| 14:48.04 | AchiestDragon | yes , as we want the board to opperate faster the main problem is the loss of the .1" pitch cable |
| 14:48.42 | AchiestDragon | so the use of the .05" pitch cable is better suited |
| 14:52.20 | AchiestDragon | but to use it means a diferent style connector from the board to an adaptor board with the socket to connect directly to the jtag port beeing tested |
| 14:54.38 | vmaster | well, having to use adapter boards is quite likely, looking at all the different layouts |
| 14:55.46 | AchiestDragon | yes so not a big problem that way if the cable connector to the adaptor and the jtag test board are diferent |
| 14:56.48 | AchiestDragon | http://www.farnell.com/datasheets/66315.pdf < this seems sutable |
| 15:31.17 | ka6sox | yawn |
| 15:34.20 | ka6sox | its too early to be up |
| 15:34.33 | AchiestDragon | :) |
| 15:35.54 | ka6sox | mawnin AchiestDragon |
| 15:36.06 | ka6sox | (thats Cajun for good morning) |
| 15:37.13 | ka6sox | AchiestDragon, I read the backlog and am worried about the same thing |
| 15:37.30 | ka6sox | obviously we could save some pins if we used a smaller connector. |
| 15:37.42 | *** join/#openjtag GyrosGeier (n=richter@p5499786A.dip.t-dialin.net) |
| 15:37.52 | ka6sox | but a 10 pin might not be the right connector |
| 15:38.08 | ka6sox | we also need at least a common ground for the boards. |
| 15:38.18 | ka6sox | so that would be 12 pins |
| 15:38.43 | ka6sox | the LVDS certianly would be very fast (think U320 SCSI) |
| 15:39.10 | ka6sox | when we crank up the speed think Terminations. |
| 15:39.33 | AchiestDragon | well theres 10 , 12, 16 and 20 pin jtag connectors in use , so we are going to need an adaptor at the end of the cable anyway |
| 15:40.14 | ka6sox | right |
| 15:40.37 | ka6sox | the current adapter (which can eventually be changed) is a 40 pin DIP one. |
| 15:40.57 | ka6sox | that can change after we test. |
| 15:41.30 | AchiestDragon | if we drove the jtag port directly from the fpga , we would lose the 2.5ns buffer delay , but lose the protection that the buffers offer |
| 15:43.02 | AchiestDragon | there could still be auto voltage setting , but may need the fpga to be configured to use them right ,, will have to read the data for the fpga see if that would be ok |
| 15:44.28 | ka6sox | I think that we need to keep the buffers there |
| 15:44.37 | AchiestDragon | yes |
| 15:44.55 | ka6sox | the auto voltage and driving capability of the driver chip is very important |
| 15:46.14 | AchiestDragon | not a problem , there maybe a problem with delays on the buffers , been reading the data for them |
| 15:46.53 | ka6sox | okaiy |
| 15:47.12 | ka6sox | unfortunately today is an early work day so I must go now. |
| 15:47.17 | ka6sox | back in 4hrs. |
| 15:49.24 | AchiestDragon | k |
| 15:49.26 | *** join/#openjtag velinp (n=velinp@c88-163.cable.netissat.bg) |
| 16:00.45 | velinp | ka6sox: ping |
| 16:05.06 | vmaster | [16:47] < ka6sox> unfortunately today is an early work day so I must go now. |
| 16:05.06 | vmaster | [16:47] < ka6sox> back in 4hrs. |
| 16:05.10 | vmaster | that was 15 minutes ago |
| 16:05.46 | velinp | vmaster: thanks |
| 16:43.25 | [g2] | lennert hey |
| 17:31.28 | velinp | [g2]: ping |
| 17:36.48 | [g2] | velinp pong |
| 17:37.02 | [g2] | velinp waazz up ? |
| 17:37.29 | velinp | hi; i'm preparing to replace redboot (hdw not yet ready :( ); which mtdblock on a nslu2 is redboot in? |
| 17:38.47 | [g2] | velinp do you have confirmed JTAG ? |
| 17:39.13 | velinp | [g2], no; I only intend to read the mtd, not write it ): |
| 17:39.46 | [g2] | well replacing RedBoot would be writing it in my book |
| 17:40.21 | velinp | [g2], ?? |
| 17:40.26 | vmaster | hence the preparing, i guess |
| 17:40.41 | vmaster | i.e. he just wants to read it to have a backup |
| 17:40.49 | velinp | yes, I want to play safe |
| 17:41.36 | velinp | and read in yesterday's log that maybe a byte/word swap was necessary; is it? |
| 17:42.00 | velinp | I mean if I need to reflash the readboot later |
| 17:42.35 | [g2] | the kernel console output prints out the partitions |
| 17:42.44 | [g2] | it's the first one numbered 0 |
| 17:43.04 | [g2] | so, dd if=/dev/mtdblock0 of=redboot.bin |
| 17:43.17 | [g2] | backs up your Redboot to the file redboot.bin |
| 17:43.41 | velinp | it is 256K, md5 is 3785ddc9def010c8ab108855fce0d9ca, but it includes my MAC? |
| 17:43.48 | [g2] | it is VERY IMPORTANT to check the if versus the of !!! |
| 17:44.04 | [g2] | yeah near the end |
| 17:44.33 | [g2] | I think the first 254+K are identical for all NSLU2 users |
| 17:44.55 | [g2] | it's probably only the last 100/140 bytes that are different |
| 17:46.18 | velinp | my md5 on the first 254 K is f063eb7f8c77d3e38bf250d25edf3a1b; could you confirm (as I only have 1 slug) |
| 18:09.06 | [g2] | velinp I haven't touched the slugs in 4-5 months... I'm running the Loft |
| 18:10.53 | velinp | [g2]: ok, thanks and good luck with the loft; do you think beewoolie might be able/willing to help me? |
| 18:11.46 | [g2] | velinp as in openslug |
| 18:12.12 | velinp | yes, i am |
| 18:35.25 | *** join/#openjtag dwery (n=dwery@nslu2-linux/dwery) |
| 18:36.03 | *** join/#openjtag beewoolie-afk (n=beewooli@206.124.142.26) |
| 18:41.40 | velinp | beewoolie: hi; care to help me verify the redboot image I dumped off mtdblock0 ? |
| 18:44.09 | *** join/#openjtag Tiersten (n=tman@nslu2-linux/Tiersten) |
| 18:55.27 | beewoolie-afk | velinp: I'm not sure I can help. |
| 18:55.56 | beewoolie-afk | You can pull the redboot image from an openslug flash image. |
| 18:57.50 | velinp | beewolie-afk: i have done upslug -u several times; i thought it did not touch redboot |
| 19:04.44 | prpplague | beewoolie-afk: hey hey |
| 19:04.48 | beewoolie-afk | poenhey |
| 19:04.48 | prpplague | beewoolie-afk: whats cookin? |
| 19:04.51 | beewoolie-afk | hey.. |
| 19:04.56 | prpplague | hehe |
| 19:04.59 | beewoolie-afk | Been hacking on the JTAG flash code. |
| 19:05.03 | beewoolie-afk | It's coming along. |
| 19:05.06 | prpplague | beewoolie-afk: cool |
| 19:05.27 | beewoolie-afk | My goal, for the moment, is to determine how fast I can flash this way using a parallel port JTAG interface. |
| 19:05.35 | beewoolie-afk | This will give me a baseline for comparison. |
| 19:05.41 | prpplague | beewoolie-afk: cool |
| 19:09.19 | beewoolie-afk | prpplague: et tu? |
| 19:17.00 | prpplague | beewoolie-afk: finally got full RW access to buildroot,busybox,uclibc and such, so i've been uploading a ton of fixes |
| 19:17.51 | prpplague | beewoolie-afk: trying to get rid of this legacy usb issue, its like a nasty bugger on my finger, just can't seem to get rid of it |
| 19:21.10 | beewoolie-afk | bummer |
| 19:21.36 | prpplague | beewoolie-afk: probably get you a patch saturday after noon for the s3c2410 |
| 19:21.50 | prpplague | beewoolie-afk: and then sunday probably the mmc/sd patch for the lnode80 |
| 19:21.56 | beewoolie-afk | np. |
| 19:22.20 | prpplague | beewoolie-afk: i'm getting ready to check in apex to buildroot |
| 19:22.33 | beewoolie-afk | Awesome! |
| 19:23.27 | beewoolie-afk | BTW, Voodoo_Z flashed apex into his slug and finds that it works. It boots faster than RedBoot, so he was motivated to use it. |
| 19:24.08 | prpplague | hehe |
| 19:24.27 | prpplague | beewoolie-afk: well if you have any busybox,buildroot issues, let me knwo |
| 19:24.39 | beewoolie-afk | Not at the moment. |
| 19:24.55 | beewoolie-afk | I have been interested in uclib, but it's too low priority for me to get into it. |
| 19:30.54 | prpplague | beewoolie-afk: buildroot works great |
| 19:31.02 | prpplague | beewoolie-afk: i add the lnode80 to the build |
| 19:31.13 | prpplague | beewoolie-afk: so adding the other lh7952x devices would be easy |
| 19:31.21 | beewoolie-afk | That isn't what I'm looking for. |
| 19:31.31 | beewoolie-afk | I'd like to build a uclib toolchain for the Sharp BSp. |
| 19:31.37 | prpplague | beewoolie-afk: right |
| 19:31.41 | prpplague | beewoolie-afk: thats what this does |
| 19:31.54 | beewoolie-afk | It's just that I've been lazy about updating the BSP to cope with anything other than crosstool. |
| 19:32.02 | prpplague | beewoolie-afk: ahh |
| 19:32.15 | beewoolie-afk | as I wrote, it's very low priority. |
| 19:32.28 | beewoolie-afk | If someone wants a small development system, they can experiment on their own. |
| 19:32.39 | beewoolie-afk | I mean, small runtime. |
| 19:32.47 | prpplague | yea |
| 19:33.07 | prpplague | well like i said its as easy as pie to do, not like getting OE running |
| 19:33.47 | beewoolie-afk | I looked at buildroot when I wrote the BSP. I don't recall why I chose not to use it. There was a show stopper there somewhere. |
| 19:34.17 | beewoolie-afk | and believe me, I'd have used someone else's solution if I could have. |
| 19:40.24 | prpplague | hehe |
| 19:43.02 | beewoolie-afk | Damn redboot. Their network code is quite buggy. |
| 20:37.44 | *** part/#openjtag velinp (n=velinp@c88-163.cable.netissat.bg) |
| 21:22.16 | ka6sox-office | ugh...back from the mines |
| 21:50.38 | beewoolie-afk | lennert: ping? |
| 23:00.56 | lennert | pong |
| 23:03.07 | lennert | beewoolie-afk: pong |
| 23:04.17 | *** join/#openjtag Tiersten (n=tman@nslu2-linux/Tiersten) |
| 23:04.24 | [g2] | lennert hey |
| 23:05.29 | [g2] | lennert I'll be getting a spec for the Parallel FPGA dongle next week and a can get several devices |
| 23:06.49 | lennert | okay, cool |
| 23:06.55 | lennert | what do they cost each? |