| 01:17.30 | *** join/#openjtag vmaster_ (i=vmaster@p549B543E.dip.t-dialin.net) |
| 03:29.43 | *** join/#openjtag bullet (n=bullet@17.60.76.83.cust.bluewin.ch) |
| 06:05.49 | *** join/#openjtag ka6sox (n=ka6sox@nslu2-linux/ka6sox) |
| 06:12.08 | ka6sox | ~lart ka6sox |
| 06:12.16 | ka6sox | heh |
| 07:30.16 | *** join/#openjtag AchiestDragon (n=dave@whipy.demon.co.uk) |
| 10:01.33 | *** join/#openjtag beewoolie-afk (n=beewooli@206.124.142.26) |
| 10:02.12 | beewoolie-afk | vmaster_: are you on by chance? |
| 10:03.49 | beewoolie-afk | ho hum |
| 13:00.53 | *** join/#openjtag prpplague (n=billybob@72.22.141.137) |
| 14:02.48 | *** part/#openjtag NAiL (n=repvik@nslu2-linux/pdpc.active.repvik) |
| 14:59.56 | *** join/#openjtag ByronT-Away (i=byron-po@nslu2-linux/ByronT) |
| 15:01.36 | ka6sox | yawn |
| 15:02.01 | prpplague | don't start taht |
| 15:02.07 | prpplague | or we will all be yawning |
| 15:05.42 | ByronT | too late |
| 15:05.47 | ByronT | need coffee |
| 15:05.52 | ByronT | need more coffee |
| 15:05.55 | ByronT | bbl |
| 15:06.44 | ByronT | dark?!? only dark?!?! if the spoon can't stand up by itself in the middle, I don't want it! |
| 15:06.56 | ByronT | coffee needs to be crunchy |
| 15:06.59 | ka6sox | mmmm |
| 15:07.06 | prpplague | more like cut it with a pair of scissors after finish pooring |
| 15:07.10 | ka6sox | now I'm back from the coffee maker |
| 15:07.41 | ByronT | I have thought about using coffee grinds like a tobacco dip |
| 15:07.51 | ka6sox | thick and Sweet. |
| 15:08.01 | ka6sox | like when I was in brazil |
| 15:08.40 | ka6sox | thats what they serve on the boats going up and down the Amazon. |
| 15:12.03 | ByronT | ahhhhhh |
| 15:12.10 | ByronT | I can feel my eyes dilating |
| 15:12.46 | ByronT | crunchy coffee... breakfast of champions |
| 15:13.34 | ka6sox | heh |
| 15:13.39 | ka6sox | hi ByronT |
| 15:13.47 | ByronT | morning |
| 15:14.03 | ka6sox | round2 |
| 15:14.17 | ByronT | how'd things go yesterday? |
| 15:14.28 | ka6sox | he still hasn't opened his eyes |
| 15:14.35 | ka6sox | we will see if he does today ;) |
| 15:14.51 | ka6sox | yesterday was a cryfest. |
| 15:15.01 | ByronT | but doctors said everything went well? |
| 15:16.07 | ByronT | I can only imagine - parenthood seems to be payback for all the times that our parents told us that we were doing something and it hurt them and we laughed at it |
| 15:19.44 | ka6sox | we shall see if it went well or not |
| 15:19.48 | ka6sox | I'm not sure yet |
| 15:20.34 | ka6sox | I have to leave in 10 minutes so let me get my second cup down and get things moving on at least 1/2 the cylinders. |
| 15:20.46 | ka6sox | back about 1.5hrs |
| 15:20.49 | ByronT | talk at ya later |
| 15:21.08 | prpplague | ka6sox: got a new critter in the house? |
| 15:24.27 | ka6sox | prpplague, got a 4yr old who had eye surgery yesterday morning |
| 15:24.56 | prpplague | oh shoot |
| 15:25.06 | prpplague | ka6sox: anything major? |
| 15:26.18 | ByronT | prpplague: just a general note... "minor surgery" is surgery to anyone not related to oneself... ;) |
| 15:28.51 | prpplague | ByronT: i see |
| 15:36.03 | [g2] | hey lennert I'm behind on my write-up :( |
| 15:37.50 | lennert | [g2]: :-( |
| 15:37.57 | ka6sox | prpplague, he had surgery for lazy eye |
| 15:38.02 | prpplague | ahh |
| 15:38.26 | [g2] | lennert I'll get to it late today or tomorrow |
| 15:38.26 | prpplague | ka6sox: wish i could get a surgery for my sons "lazy ass" |
| 15:38.46 | [g2] | the good thing is things are moving along |
| 15:39.13 | lennert | [g2]: looking forward |
| 15:53.15 | wookey__ | prpplague: rotfl |
| 15:54.50 | prpplague | wookey__: hehe, trying to break him of it early |
| 16:08.27 | prpplague | wookey__: don't suppose to met up with pb_ very often since you guys are in the same neighborhood |
| 16:08.37 | prpplague | s/to/you |
| 16:38.21 | *** join/#openjtag velinp (n=velinp@c88-163.cable.netissat.bg) |
| 16:46.58 | wookey__ | prpplague: we meet occaisionally, and at events of one sort or another. Last year we were on the same project and met loads |
| 16:47.21 | wookey__ | actually, no year before - bloody hell - where does the time go? |
| 16:47.40 | prpplague | wookey__: ahh , hehe, it definetly disappears rather quickly |
| 17:02.38 | AchiestDragon | has anyone got the schematics for the proposed interface ? |
| 17:27.39 | ka6sox | they might be in CVS |
| 17:27.52 | ka6sox | check out the openjtag CVS at SF.net |
| 17:28.42 | AchiestDragon | k |
| 17:29.31 | velinp | hi; ka6sox: just wanted to tell you I sent a summary of our discussion (adding SDRAM on NSLU2) to nslu2-linux, #10838. ok? |
| 18:00.04 | *** join/#openjtag dwery (n=dwery@nslu2-linux/dwery) |
| 18:30.48 | AchiestDragon | been having a think , with a xilinx xc3s250 it should be posible to use a ip core for the usb rather than needing a ftdi chip and as the xc3s250 has configerable i/o then should be possible to set the i/o voltage levels |
| 18:32.20 | lennert | xc3s200 you mean? |
| 18:32.26 | AchiestDragon | so the jtag interface module would just need a usb buffer , fpga and sdram chip and a config device , and the usual other bits like conectors and psu |
| 18:32.29 | lennert | or xc3s400 |
| 18:32.37 | lennert | i don't think there is a -250 |
| 18:32.45 | lennert | (but i could be mistaken..) |
| 18:33.49 | AchiestDragon | well the xilinx site in the data says 250 but that could be a missprint as the closest i have the footprint and part info for in dxp is the 200 |
| 18:36.04 | AchiestDragon | http://direct.xilinx.com/bvdocs/publications/ds312.pdf this says they do 100, 250, 500, 1200 and 1600 vesions but doesnt match what is avalable |
| 18:36.20 | lennert | the datasheet for the spartan3 is ds099.pdf |
| 18:36.51 | lennert | this is the spartan3e |
| 18:37.00 | lennert | different beast |
| 18:37.00 | AchiestDragon | yes |
| 18:37.03 | AchiestDragon | k |
| 18:37.04 | lennert | xc3s250e, not xc3s250 |
| 18:37.07 | lennert | okay |
| 18:38.23 | AchiestDragon | althoug in a 100 pin package the pinouts are the same for the 100 and 250 versions , just internal capacaty thats diferent |
| 18:38.48 | lennert | that's the same in any fpga |
| 18:38.57 | lennert | there are typically 2 or 3 capacities for the same pinout |
| 18:39.05 | lennert | and 2 or so pinouts for a single capacity |
| 18:39.10 | lennert | so that you have an upgrade path |
| 18:40.49 | AchiestDragon | well with a 32mb *8bit sdram theres 33 i/o pins to play with |
| 18:42.07 | AchiestDragon | so 2 for the usb , 2 that are going to endup on a bank with a set volatage as other pins on it need 3.3v |
| 18:42.34 | AchiestDragon | leaving 4 banks to play with |
| 18:44.11 | AchiestDragon | so could manage jtag on one bank leaving 3 banks so could even suport an alternate host i/f like parallel port |
| 18:44.57 | AchiestDragon | or rs232 with the right buffers , or maybe use the extra inputs for logic analizer functions |
| 18:51.07 | AchiestDragon | the only xilinx fpga i have had an indepth look at is the vertex pro xc2vp20 , that allowed a function that part of the device could be reprogramed while the rest was opperational |
| 18:51.33 | lennert | partial reconfig |
| 18:51.42 | AchiestDragon | yes |
| 18:51.47 | lennert | i have some xilinx cplds, an xc3s200 and an xc2vp30 |
| 18:52.06 | AchiestDragon | do you know if the smaller parts do |
| 18:55.46 | lennert | the sp3 can do partial reconfig, i think |
| 18:55.50 | lennert | but i'm not 100% sure -- check ds099 |
| 18:56.03 | AchiestDragon | k |
| 18:58.11 | *** join/#openjtag Tiersten (n=tman@nslu2-linux/Tiersten) |
| 19:02.32 | AchiestDragon | the only disadvantage i can see in using a fpga , is the inital programming of the config for the board , since this is a jtag test and programming device its a bit bad if you need to build a programmer to program it in the first instance |
| 19:03.23 | lennert | use a prom.. |
| 19:03.34 | lennert | or do usb firmware download |
| 19:04.10 | AchiestDragon | still need a prom programer , usb download would be a better option but would still need a usb chip |
| 19:05.20 | lennert | you can progam xilinx proms with jtag |
| 19:06.19 | AchiestDragon | catch 22 , how do you initaly program your jtag programmer with jtag ? when that is the only programmer you have |
| 19:06.44 | lennert | you let someone else make the board |
| 19:07.08 | lennert | that's like saying that c sucks because the c compiler is written in c -- you download someone else's binary |
| 19:08.02 | AchiestDragon | well i gues if your building this board then you may already have a means to program the device |
| 19:08.20 | lennert | you should.. |
| 19:23.08 | *** join/#openjtag GyrosGeier (n=richter@p549948AF.dip.t-dialin.net) |
| 19:45.18 | AchiestDragon | if it offers both usb and parallel port options for linking it to a pc then it could be initaly programmed up using the parallel port |
| 20:27.16 | *** join/#openjtag beewoolie-afk (n=beewooli@206.124.142.26) |
| 20:29.16 | vmaster_ | hey beewoolie-afk - missed you for about 5 minutes this morning |
| 20:33.46 | beewoolie-afk | vmaster: |
| 20:34.04 | beewoolie-afk | vmaster: I was just wondering if you would be on so late...my time. |
| 20:34.12 | beewoolie-afk | I have a question about your openocd project. |
| 20:34.55 | vmaster | heh, it was 11am for me, so yeah, usually i would be on |
| 20:36.02 | beewoolie | I was reading the arm9tdmi.c file and found something that I couldn't explain. Granted, that my overall comprehension of the code is limited. |
| 20:36.27 | prpplague | beewoolie: hey hey bud |
| 20:36.31 | prpplague | beewoolie: whats cookin? |
| 20:36.37 | beewoolie | In arm9tdmi_examine_debug_reason(), there is a call to jtag_add_dr_scan without calling jtag_execute_queue afterward. |
| 20:36.43 | beewoolie | Is this OK? |
| 20:36.49 | beewoolie | prpplague: yo. |
| 20:37.10 | vmaster | yeah, the second dr scan doesn't have to be executed immediately |
| 20:37.23 | vmaster | i'm trying to build command buffers as large as possible for the ft2232 |
| 20:37.52 | beewoolie | I wondered because it references a stack variable as an output, but the function returns before it can be processed. |
| 20:38.27 | vmaster | out values are copied |
| 20:38.43 | vmaster | out is host->device |
| 20:38.49 | beewoolie | I mean outputs *from* the target. |
| 20:39.09 | vmaster | the in_value of all three fields is set to NULL |
| 20:39.17 | vmaster | before the second dr_scan |
| 20:40.19 | beewoolie | OK. I see what you mean. The fact that debug_reason is a reference made me think that it was returning a value. |
| 20:40.46 | vmaster | ah, i see |
| 20:42.13 | vmaster | the output values are copied inside jtag_add_dr_scan, so the calling code doesn't have to take care about this any more |
| 20:44.30 | *** join/#openjtag khem (n=khem@gateway-1237.mvista.com) |
| 20:50.14 | AchiestDragon | the ftdi 2232 has a eeprom interface , that can be configured over the usb , is wondering if theres a way to trick it into using a bigger device that could initalize a fpga with a bit of crafty interfacing |
| 20:50.42 | beewoolie | prpplague: Are you back to some dev work? |
| 20:50.48 | ka6sox-office | I"ve looked at that...the algorithm isn't avalilable for it (as far as I can tell) |
| 20:50.55 | prpplague | beewoolie: yep, actually testing apex now |
| 20:51.18 | ka6sox-office | AchiestDragon, I only have a windows config program. |
| 20:51.28 | beewoolie | Have you tried enabling the MMU? |
| 20:51.50 | AchiestDragon | will it run in wine ? |
| 20:52.01 | ka6sox-office | AchiestDragon, haven't tried |
| 20:52.43 | ka6sox-office | I plan on having the FPGA separate from the interface |
| 20:52.52 | ka6sox-office | and if possible using Ethernet |
| 20:53.04 | ka6sox-office | ala BDI |
| 20:53.19 | AchiestDragon | k |
| 20:53.38 | AchiestDragon | so 2 difernt hardware methods |
| 20:54.24 | ka6sox-office | the interface board that ep1220 designed should be used as it provides all the various voltage/connector configurations. |
| 20:54.52 | ka6sox-office | the S3e board will be used for Memory/Programming/Breakpoint stuff |
| 20:55.09 | AchiestDragon | is that using the dlp 40 pin dip module |
| 20:55.44 | ka6sox-office | there is a connector on the S3e board that should be easy to adapt to the 40pin DIP |
| 20:56.55 | ka6sox-office | brb |
| 20:57.10 | beewoolie | prpplague: the I'm curious of the MMU enabling code works on your targets. |
| 20:57.17 | AchiestDragon | k, personaly from past experiances i would use the chip , but not take advantage of the evaluation module , evaluation modules have a habit of only beeing avalable for a short time , 6 months to 2 years |
| 20:57.26 | prpplague | beewoolie: ahh |
| 20:57.34 | prpplague | beewoolie: i'll have to test that tomorrow |
| 21:01.47 | AchiestDragon | bbl |
| 21:02.12 | ka6sox-office | AchiestDragon, by that time we could move on to a "custom" board |
| 21:02.27 | ka6sox-office | a custom board would be very expensive for prototyping. |
| 21:02.40 | ka6sox-office | (the interface is "custom" so we still need that. |
| 21:02.43 | ka6sox-office | ) |
| 21:02.57 | AchiestDragon | not too bad , it can be done easy |
| 21:03.42 | AchiestDragon | about £15 for a 100*160mm pcb (dubble sided ) in 1 offs |
| 21:04.20 | AchiestDragon | and it looks like you could get 4 or more on a pcb that size |
| 21:06.05 | AchiestDragon | if 4 layers are needed , in the next 4 to 5 months i am getting a 4 layer pcb made for another project only using 100mm*100mm so have 60*100mm left for another project atm |
| 21:06.24 | AchiestDragon | back in 30 mins |
| 21:07.13 | ka6sox-office | AchiestDragon, cya then |
| 23:03.25 | beewoolie | vmaster: I've got another question for you if you're listening. |
| 23:03.51 | ka6sox-office | AchiestDragon, ping? |
| 23:04.05 | AchiestDragon | 2 mins ,,, pong |
| 23:04.52 | *** join/#openjtag key2 (n=key2@gob75-2-81-56-64-17.fbx.proxad.net) |
| 23:04.55 | key2 | yop |
| 23:04.59 | key2 | lennert: there ? |
| 23:05.07 | AchiestDragon | k ,,back |
| 23:07.18 | *** join/#openjtag dwery (n=dwery@nslu2-linux/dwery) |
| 23:10.16 | key2 | someone has tryed to run a linux on a xilinx (xc2VP30) ? |
| 23:11.08 | *** join/#openjtag ByronT-Away (n=byron-po@nslu2-linux/ByronT) |
| 23:12.18 | AchiestDragon | yes , afik , it will run linux , with the right hardware config , that has a ppc core built in |
| 23:14.09 | AchiestDragon | there was on of there evaluation boards that ran linux using one in that series of fpga's |
| 23:15.25 | AchiestDragon | down side was there tool set for configureing the fpga the free ones did not support the vertex pro chips so a $4000 for the software that would |
| 23:21.38 | ka6sox-office | ya...there is cheaper but I'm looking at "other" cores. |
| 23:21.50 | ka6sox-office | Leon :) |
| 23:27.41 | AchiestDragon | ka6sox-office: if the design is funtional using the eval boards im willing to redo the pcb artwork so its a compleate single custom board option , and should be able to build 1 or 2 test versions of it |
| 23:29.14 | key2 | AchiestDragon: what do you use for makin pcb ? |
| 23:29.53 | AchiestDragon | been having a quick look and may be able to get it into 50mm*50mm ( for a fpga version with sdram ) on 4 layers , and easy within 60*100 on dubblesided |
| 23:30.25 | key2 | AchiestDragon: yeah but what software do you use for makin you pcb? |
| 23:30.27 | AchiestDragon | protel dxp , for the cad , i use a company called ecp circuts to make them |
| 23:30.40 | key2 | ecp circuit ? |
| 23:30.44 | key2 | they solder bga ? |
| 23:30.59 | AchiestDragon | no but make upto 16 layer pcbs |
| 23:31.00 | ka6sox-office | AchiestDragon, thanks. |
| 23:31.48 | AchiestDragon | theres another company that i would use for assembly , but for 1 or 2 i would probablay assemble them myself , unless bga |
| 23:31.56 | key2 | AchiestDragon: and how do you wanna solder a BGA on it |
| 23:32.10 | key2 | and what about BGA :) |
| 23:32.13 | key2 | i could do the rest |
| 23:32.18 | key2 | but I don't have a BGA oven |
| 23:32.31 | AchiestDragon | was not planning to use a bga |
| 23:32.34 | AchiestDragon | but |
| 23:32.46 | key2 | you know virtex that is not BGA ? |
| 23:32.48 | key2 | with PPC in it ? |
| 23:33.03 | ka6sox-office | AchiestDragon, BGA isnt' fun |
| 23:33.16 | ka6sox-office | we did BGA PPCs |
| 23:34.12 | AchiestDragon | http://www.seattlerobotics.org/encoder/200006/oven_art.htm < this works for bga packages , but expect a 40 to 60% fail rate |
| 23:34.23 | key2 | AchiestDragon: so you think I would be able to run a Linux using both PPC of the xc2vp30 (http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P) |
| 23:34.26 | key2 | ? |
| 23:34.55 | AchiestDragon | so no good for the 1700 pad bga packages as it could prove expesive |
| 23:35.39 | AchiestDragon | thay manage to run multiple cores in the ps3 in linux |
| 23:35.47 | key2 | well 299 is not that expensive |
| 23:36.12 | key2 | it's hardcore right ? |
| 23:36.22 | ka6sox-office | AchiestDragon, I don't think we need to spend that much! |
| 23:36.32 | ka6sox-office | I wasn't going to go HardCore. |
| 23:36.41 | ka6sox-office | the Dev system is toooo much |
| 23:37.05 | AchiestDragon | in the vertex yes its hard core , but we dont need anything that big for this project |
| 23:37.26 | AchiestDragon | hard core for the internal ppc's that is |
| 23:37.45 | key2 | what project :) |
| 23:37.49 | beewoolie | AchiestDragon: Looks like a great use for JTAG verification |
| 23:38.17 | AchiestDragon | and the rocket i/o would be tops for logic analizer also |
| 23:38.40 | key2 | AchiestDragon: what's the project :) share |
| 23:38.41 | AchiestDragon | 1 to 2Ghz on 6 to 24 chans |
| 23:39.36 | AchiestDragon | that was scrapped about 3 years ago , because there was no way to get the software to reconfig it on open source |
| 23:40.17 | ka6sox-office | the WebPack is a LOT better now. |
| 23:40.20 | AchiestDragon | and xilinx had no plans to relece the free web tools with a vretex pro capablility |
| 23:40.36 | ka6sox-office | they have V4 capability now |
| 23:42.35 | AchiestDragon | i designed a board that used a vertex pro 2vp20 that had one ppc core , some external fast syncronus ram 256mb at 800mhz and some i/o , with a compact flash for fpga config and system o/s bootup |
| 23:43.20 | AchiestDragon | the board was to be 6 layers , and be open hardware , but the software problem and a hardware suplyer proble stopped it |
| 23:44.13 | AchiestDragon | the ram was made by micron , but was in pre production samples at the time , micron got bought out and the ram got discontinued |
| 23:45.40 | AchiestDragon | so a large redesign , i was on version 0.9 at the time , allong with a personal problem i susspended futher development , |
| 23:46.08 | AchiestDragon | the 2vp20 was £700 in 10 offs at the time , so there cheaper now |
| 23:46.33 | ka6sox-office | is the S3e good enough? |
| 23:46.41 | ka6sox-office | or do we need the Virtex? |
| 23:47.04 | AchiestDragon | since then i found the cyclone 2 and that seems good for the price and with the free tools |
| 23:47.37 | AchiestDragon | for just jtag guess a small spartan2 or 3 should do the job |
| 23:49.10 | ka6sox-office | we want to build something that replaces a BDI2000 (at a hobbiest price :)) |
| 23:49.29 | AchiestDragon | it dosent need to run a o/s , it basicaly needs to opperate as a serial buffer to the host , so the host can pre load contents to ram , and once loaded its just blasted into the device |
| 23:49.31 | ka6sox-office | I'd like it to be about $250 |
| 23:49.52 | AchiestDragon | do you have a link for the bdi2000 |
| 23:50.30 | ka6sox-office | abatron AG |
| 23:50.31 | key2 | AchiestDragon: vhdl or verilog ? |
| 23:51.24 | ka6sox-office | http://www.abatron.ch/ |
| 23:52.00 | AchiestDragon | me , not managed ether yet , still working on desining a hardware platform , but dxp lets me enter in schematic form , and get the idea of both |
| 23:52.53 | key2 | AchiestDragon: where you from ? |
| 23:53.01 | AchiestDragon | uk |
| 23:53.11 | key2 | k |
| 23:54.27 | key2 | by the way, someone knows a solution for reading/programming a flash rom onboard |
| 23:54.32 | key2 | without unsoldering it from the board ? |
| 23:54.59 | key2 | like something you plugg on the flash rom and it touches all its pins ? |