| 00:52.43 | *** join/#openjtag ByronT (n=byron-po@nslu2-linux/ByronT) |
| 01:17.38 | *** join/#openjtag vmaster_ (i=vmaster@p549B53E8.dip.t-dialin.net) |
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| 13:07.53 | prpplague | morning folks |
| 13:09.26 | velinp | <PROTECTED> |
| 13:10.02 | velinp | ka6sox, ka6six-office: ping |
| 13:18.47 | vmaster | that's because 4:30 is 4 hours too early |
| 13:23.00 | prpplague | i normally prefer to work from like 10am to 9pm but the company i work for really doesn't revolve around those time frames |
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| 15:40.57 | velinp | ka6sox, ka6sox-office: ping |
| 16:01.02 | wookey__ | [g2]: just got an answer from my XJTAG assistant |
| 16:01.17 | wookey__ | It costs GBP 9000 |
| 16:01.31 | wookey__ | but they do good deals for academic institutions |
| 16:01.46 | wookey__ | it runs at about 10Mhz, which means all the balloon2 test take < 10 seconds |
| 16:01.53 | wookey__ | The good bits are: |
| 16:02.14 | wookey__ | - a live 'XJAnalyzer' view of all the pins with customisable watches and |
| 16:02.15 | wookey__ | manual twiddling, pulsing and so on |
| 16:02.19 | wookey__ | - completely automated testing for shorts and opens as far as possible |
| 16:02.28 | wookey__ | - a very cunning level of abstraction of boards into reusable devices |
| 16:02.29 | wookey__ | via a slightly unpleasant language, XJEase. |
| 16:03.05 | wookey__ | (so XJEase lets you easily write a suite of tests at a reasonably high level) |
| 16:15.04 | [g2] | oops |
| 16:16.20 | [g2] | wookey__ I've got a FGPA based approach that will run at 10MHz clock rate |
| 16:16.39 | [g2] | well I've got access to one :) |
| 16:17.53 | [g2] | I think the netlist processing will take some work, but I think it's all pretty straight forward |
| 16:18.20 | [g2] | it'll also take a little while to get the graphics pretty, but they'll work |
| 16:20.03 | [g2] | 10 seconds seems kinda fasts |
| 16:20.16 | [g2] | s/fasts/fast/ |
| 16:21.08 | [g2] | you are checking for shorts but are you bringing up external devices ? |
| 16:21.24 | [g2] | or doing that with SW tests |
| 16:22.55 | [g2] | wookey__ In my mind there are a couple target areas to address |
| 16:23.50 | [g2] | 1) is the capabilities to address the functional testing and it can start out custom to start, i.e., a V3 or V2 board and it's hand crafted |
| 16:24.35 | [g2] | 2) General tools like the 'analyzer' that allows testing on things like PXA27x chips or IXP42x chips |
| 16:25.00 | [g2] | 3) the tool generators that build it all and automate it all |
| 16:25.20 | [g2] | 4) extensions to special cases that 3) can't address |
| 16:32.45 | AchiestDragon | hmm |
| 16:33.44 | AchiestDragon | http://www.minford.ca/html/mf1500aadapter.html i have one of these , not got round to trying it out as yet , but think it uses the jtag method |
| 16:35.17 | GyrosGeier | the interesting part of any JTAG adapter is not the hardware, but the software libraries it uses on the target |
| 16:35.34 | GyrosGeier | the hardware can be easily built, e.g. with the FTDI chips |
| 16:35.50 | AchiestDragon | its a simple little circuit using a 74hc244 and some resistors |
| 16:37.19 | AchiestDragon | maybe ok for most jtag stuff but think it would be a bit slow for the real time pin state display |
| 16:40.30 | AchiestDragon | thinking about it from a tools point of view , was reading a artical recently on the xbox380 linux project , |
| 16:41.23 | AchiestDragon | they were using xilinx devices configured to form a logic analizer allowing high speed opperation |
| 16:42.36 | AchiestDragon | guess maybe it could be posible to use a fpga itself with some interface like usb or ethernet to allow the unit to opperate at a faster speed than 10mhz |
| 16:43.14 | GyrosGeier | AchiestDragon, the biggest problem with both USB and Ethernet is its RTT |
| 16:44.02 | GyrosGeier | AchiestDragon, that's why a sane controller will be able to do bulk transfers on its own, without help from the host |
| 16:44.53 | GyrosGeier | AchiestDragon, ideally, the block sizes are very large, or there is some kind of windowing technique (i.e. asynchronous error reporting) |
| 16:44.59 | AchiestDragon | using a ram buffer and some trigger signal detection , detecting a time slice and beeing able to analize a period of time is as useful as a continus readout |
| 16:47.54 | AchiestDragon | and unless the jtag will opperate at number of i/opins * i/o clock your not going to get a true readout of the pin state , that would put the jtag spec above the chips max ferquancy |
| 16:48.46 | vmaster | you're usually not interested in a true readout - if you are, you use a logic analyzer |
| 16:48.58 | AchiestDragon | true |
| 16:52.18 | [g2] | GyrosGeier there are several kernel hackers in here and plenty of sw types |
| 16:52.48 | [g2] | IMHO there are 2 main roadblocks |
| 16:53.05 | vmaster | i guess GyrosGeier comes from the "debug" side of jtagging |
| 16:53.27 | [g2] | 1) Access to cheap fast JTAG hw which is why this group is formed |
| 16:55.05 | GyrosGeier | well, even for the profiling side of JTAG you want an intelligent board |
| 16:55.21 | [g2] | 2) the programming skills and tools for the FPGA that's probably used in one |
| 16:56.10 | [g2] | So I think 1 well be significantly moved forward in the next few weeks |
| 16:56.45 | [g2] | and I think that we are getting closer to 2 or there may be a basis for start with a roadmap allowing updates |
| 16:57.35 | AchiestDragon | 1 is a problem that there are a number of easy solutions to if 2 can be made to work with them |
| 16:58.24 | [g2] | AchiestDragon I'm talking about 10Mhz+ capable devcies that are cheap |
| 16:58.49 | vmaster | [g2]: it's not only the tck rate, but the interface provided to the software layer |
| 16:59.24 | AchiestDragon | http://www.opencores.org/projects.cgi/web/ethdev/overview <this may be a bit overkill but would itself make a good jtag programmer /test environment |
| 16:59.33 | [g2] | vmaster you are absolutely right, however it's < $20 gets you an extra 600K gates so that's not really the issue |
| 16:59.48 | [g2] | the issue is the code associated with those 600K gates |
| 17:00.04 | vmaster | ohhh |
| 17:00.13 | AchiestDragon | thers a usb fpga open hardware project on there also |
| 17:00.45 | [g2] | I've talked to the vendor that builds the Loft boards |
| 17:01.10 | [g2] | They can also build a little FPGA device. |
| 17:01.34 | AchiestDragon | having a fpga programed for the task would program other fpga devices , and could posiblay offer some i/o configured as logic analizer inputs for use also |
| 17:01.37 | GyrosGeier | it might be the sanest idea to get a Cypress or something like that to do the USB side and provide intelligence, and do only really time-critical stuff in the FPGA |
| 17:02.13 | [g2] | I had preliminary discussions Friday and it's possible to have devices in the not too distant future as it's pretty simple |
| 17:02.26 | GyrosGeier | which is what Amontec have done |
| 17:02.38 | GyrosGeier | (minus the USB stuff) |
| 17:02.58 | [g2] | one approach discussed was the CY068 and S3 |
| 17:03.04 | AchiestDragon | or this http://www.opencores.org/projects.cgi/web/maxii-evalboard/overview |
| 17:04.58 | AchiestDragon | i have been working on a fpga board http://www.whipy.demon.co.uk/fpga1.zip , but |
| 17:06.02 | AchiestDragon | just had a major system crash and the windows box with my cad on is down , and lost the data , so got to restart |
| 17:07.55 | AchiestDragon | but should be easy enough to come up with a custom pcb for jtag prgramming test using a fpga , and get it posted on open cores , if i can get windos to reinstall on the machine |
| 17:08.00 | *** join/#openjtag ByronT (i=byron-po@nslu2-linux/ByronT) |
| 17:08.41 | [g2] | AchiestDragon I think putting the code on OC is a great idea |
| 17:09.14 | [g2] | However, it don't think OC has the stuff we are looking for (I may be totaly wrong) |
| 17:09.48 | [g2] | I'm not looking to get a big group discussing lots of different capabilities (we've done that here for quite some time) |
| 17:10.14 | [g2] | I'm interested in building a product that I can use, another friend can use for his boards, and wookey__ with the V3 |
| 17:10.25 | AchiestDragon | i'm mainly hardware design rather than software , and want to learn how to program fpga's , but like you seem to have found cost is the problem |
| 17:11.05 | [g2] | well I think the BDI solutions and Abatron are like $2500 US |
| 17:11.16 | [g2] | then each processor family is more |
| 17:11.38 | vmaster | you get one processor family with the 2500 |
| 17:11.39 | prpplague | yea |
| 17:11.42 | [g2] | Like 1.5K for ARM, another for Xsclae etc... |
| 17:11.47 | prpplague | as well as the laugterbach |
| 17:12.00 | AchiestDragon | the pc104 board i am doing is so i can play arround with a cyclone 2 device on my arm sbc |
| 17:12.02 | vmaster | but there's a lot more to the bdi2000 than just the hardware |
| 17:12.34 | vmaster | the target specific debugging logic is a lot work |
| 17:12.45 | vmaster | and they support almost every possible arm core for example |
| 17:12.48 | [g2] | vmaster absolutely there's a lot more |
| 17:13.32 | vmaster | the bdi's hardware is cheap - a 68332, a small cpld (32 macrocells or so), some flash and a bit sram |
| 17:13.47 | [g2] | but in my mind, a key reason this high speed professional wall hasn't been torn down is that there weren't devices avialable for the sw guys and hobbiest to go make it work |
| 17:14.13 | vmaster | definitely |
| 17:14.15 | AchiestDragon | the problem is bga packages |
| 17:14.27 | [g2] | vmaster you are right about the target specific stuff, but there are 100s of devs |
| 17:14.37 | [g2] | there's like 5 ARM guys in here |
| 17:15.02 | [g2] | beewoolie is already working on the debug stuff |
| 17:15.16 | AchiestDragon | ok so you can solder down a bga package with a toaster oven at home , but theres a 40% fail rate when you get good at it |
| 17:15.32 | [g2] | I think the XScale is about perfect as it works for IXP4xx and PXA27x |
| 17:15.56 | AchiestDragon | and multilayer pcbs are not cheep and not easy to make at home |
| 17:16.04 | [g2] | AchiestDragon I can have these build and tested professionally |
| 17:16.20 | [g2] | then everyone gets a "known good" device" |
| 17:16.34 | AchiestDragon | so can i , but theres a need for some that can be built at home |
| 17:16.35 | [g2] | and in the long run it saves tons of time and money |
| 17:16.58 | vmaster | AchiestDragon: if someone wants to build a jtag adapter at home, he uses a wiggler style parport interface |
| 17:17.51 | AchiestDragon | for production then upto 16 layer pcbs and bga packages with 1700+ pads np , but for home use there are still alot of std surface mount devices that can be used |
| 17:18.58 | AchiestDragon | the cyclone 2 in a 240pin qfp can be hand soldered with little problems at home , if you know how |
| 17:19.36 | vmaster | heh, i wont bother building this myself if g2 is able to have it built for $20 |
| 17:21.32 | AchiestDragon | for a jtag progaming then i guess a device in a 64 or 100 pin quad flat pack could be used , and probabaly on duble sided pcb , so looking at £8 to £10 for a single 1 of pcb (would probabaly get 10 for that price ) |
| 17:22.55 | AchiestDragon | plus the £ for the device and other components , in 1 offs would make it about £40 , in production guess around £15 dependent on the fpga cost |
| 17:23.17 | vmaster | what density do you get in 64 or 100 pin packages? |
| 17:23.46 | AchiestDragon | on the fpga |
| 17:23.50 | vmaster | yeah |
| 17:24.27 | AchiestDragon | ? i know thay do some in that , but i have been looking at bigger devices |
| 17:27.19 | AchiestDragon | whats needed ? |
| 17:27.52 | vmaster | i guess you'll need one of the bigger devices with enough on-chip ram bits, or external ram |
| 17:28.05 | vmaster | no matter how clever your design is, you'll need quite large buffers |
| 17:28.20 | AchiestDragon | external ram is going to be a better option |
| 17:28.43 | vmaster | yeah, but then a 2-layer pcb wont suffice, right? |
| 17:30.19 | AchiestDragon | 2 layers may be ok , will check that , depends on layout |
| 17:31.01 | vmaster | my point is this: for versatile 10mhz jtagging, a "simple" design wont be enough |
| 17:31.44 | [g2] | vmaster I'm thinking CY068 USB 2.0 device for host communications |
| 17:31.52 | [g2] | 600 or 1M gate S3 |
| 17:32.08 | [g2] | Jtag onboard for the FPGA and CY loading |
| 17:32.21 | [g2] | maybe 1 MB SRAM |
| 17:32.44 | [g2] | I guess ideally dual ported |
| 17:33.01 | [g2] | that would serve as buffers |
| 17:33.21 | vmaster | mhh, driving the fpga at twice the speed would be cheaper |
| 17:33.36 | vmaster | dual ported ram is expensive, isn't it? |
| 17:33.46 | [g2] | I dunno if any onboard storage for the FPGA is needed |
| 17:33.54 | [g2] | vmaster dunno cost |
| 17:34.51 | [g2] | We need to put a Bill of materials together with costing estimates |
| 17:35.10 | AchiestDragon | i was thinking something like a sdram , say 32mb 8 or 16 bit device |
| 17:35.47 | [g2] | AchiestDragon that's great, but I think it's overkill |
| 17:35.59 | AchiestDragon | although theres more ram there than needed , but the devices are cheeper than smaller dual port version |
| 17:36.01 | AchiestDragon | s |
| 17:36.15 | [g2] | in my mind, the problem with the OC stuff is it's very large gate wise |
| 17:36.45 | [g2] | I think we just need to look at the BW and timing a little |
| 17:37.12 | [g2] | the CY068's can sustain nearly USB 2.0 rates, lets say 30MBs |
| 17:37.45 | [g2] | so we probably don't need dual-port SRAM |
| 17:37.50 | [g2] | at least initially |
| 17:37.53 | AchiestDragon | yes , but remeber jtag devices are dasiy chained so when doing something like a board test you may be testing 5 or more devices |
| 17:38.25 | [g2] | AchiestDragon right, and that's limited by TCLK and the FPGA right ? |
| 17:38.41 | AchiestDragon | yes |
| 17:38.53 | [g2] | the shift chain on the IXP42x is 497 498 |
| 17:39.46 | [g2] | we need to start defining the OPs (operations) on the FPGA for given processors/families |
| 17:40.13 | [g2] | and some general JTAG stuff that's applicable to all |
| 17:40.45 | [g2] | there are two specific applications from my perspective |
| 17:41.00 | [g2] | 1) post-build board testing |
| 17:41.07 | [g2] | 2) General board testing |
| 17:41.32 | [g2] | I think in case 1) you know exactly what you want to test and are optimizing it |
| 17:41.51 | [g2] | it's a question of cost/time for how much you trade off |
| 17:42.58 | [g2] | I"m looking to provide myself, wookey__ and others that want to build boards with a mechansim that helps driver down the cost of those boards and drives up the quality |
| 17:43.18 | [g2] | clearly that provides value to many |
| 17:45.00 | AchiestDragon | looking at the data for the cyclone devices the bigest 144pin tqfp packaged device is a ep2c8 that has 8,256LE's and about 200k ram & 26 multiplyers |
| 17:46.41 | AchiestDragon | there is a smaller 100 pin tqfp cyclone2 with 2,910 LE's and about 72k ram , no multipliers |
| 17:46.57 | AchiestDragon | ram size in bits not bytes |
| 17:49.56 | AchiestDragon | the ep2c8t144c7 costs us$23.1 in 1 offs from altera thats the 144pin device |
| 17:51.05 | vmaster | AchiestDragon: xilinx has some major advantages: lennert and ka6sox |
| 17:53.18 | AchiestDragon | ha |
| 17:53.20 | AchiestDragon | k |
| 17:53.48 | vmaster | they know the devices and the toolchain |
| 17:56.01 | AchiestDragon | just that the xilinx devices 1 seem a bit power hungry , 2 cost more , 3 there tools are free but with a limit on the max device size , altera tools are free for all models they do |
| 17:56.27 | AchiestDragon | although some of the xilinx devices are cool |
| 17:59.28 | [g2] | AchiestDragon since many ppl are already on the Xilinx horse it'll be hard go get everyone to switch :( |
| 17:59.45 | AchiestDragon | well np |
| 18:04.58 | AchiestDragon | something like a xc3s250e is avalable in a tqfp 144pin package , 250k system gates , 5,508LE's 200kbits ram should do |
| 18:09.55 | AchiestDragon | infact this with some diferent software should do http://warmcat.com/milksop/filtror.html |
| 18:14.20 | AchiestDragon | he's got a good page showing how to solder the devices in also http://warmcat.com/milksop/soldering.html |
| 18:18.14 | AchiestDragon | his pcb is dubble sided with ram on there also , bit of reworking of it to provide buffered jtag outputs sourced from the fpga and something along the lines of that should do the job |
| 18:18.56 | AchiestDragon | and mabe add usb if needed rather than parallel port |
| 18:27.42 | ka6sox | soldering that fine of a pitch is a PITA |
| 18:27.46 | AchiestDragon | although that uses a clpd , so may be better using a true fpga , so it can be reprogramed |
| 18:28.21 | ka6sox | CPLDs are faster but a LOT smaller. |
| 18:29.29 | AchiestDragon | the method he shows for soldering works i know someone that uses it all the time , i prefer solder paste and a hot air gun |
| 18:30.14 | ka6sox | that works nice...I have the Hot Air machine too. |
| 18:34.25 | AchiestDragon | :) yes , btw the hot air guns (the type used as hot air paint strippers ) work fine also and dont cost the hobbiest anything like that of the hot air solder stations |
| 18:35.00 | ka6sox | mine was about $300 with all the nozzles but it worth it. |
| 18:35.41 | ka6sox | AchiestDragon, what are you looking to do? |
| 18:38.05 | AchiestDragon | i'm trying to build a robot , but its a long project , as i need to coordinate 40 servo motors with balance feedback i'm planning on useing a fpga as the logic for the balance feedback and i/o from the cpu |
| 18:39.11 | AchiestDragon | but as the fpga is going on a 4 layer pcb i endup with a min order of 5 pcb's so want to make the fpga board sutable for other uses |
| 18:43.05 | AchiestDragon | so end result will be a robot , but there is quite a few offshoot projects from it that will do other things also |
| 18:44.05 | VoodooZ_Work | AchiestDragon, interesting!! I'm into robotics too. I'm using the slug as my controller. |
| 18:44.25 | AchiestDragon | started from me looking at this http://warmcat.com/milksop/soldering.html open hardware project |
| 18:44.54 | AchiestDragon | there seems to be little activity there , and im not too hapy with there design |
| 18:45.09 | AchiestDragon | so im starting a new one from scratch |
| 18:46.37 | AchiestDragon | the only requirements i have set is it has to make and bring me coffee , although the make coffee bit maybe just to retreve the cup from a coffee vending machine |
| 18:47.20 | VoodooZ_Work | Keep in mind that the easiest part is the hardware! Software is much tougher! |
| 18:47.45 | AchiestDragon | and terain excludes use of wheels or tracks , so it has to walk |
| 18:47.47 | AchiestDragon | yes |
| 18:48.01 | VoodooZ_Work | ouch! |
| 18:48.15 | VoodooZ_Work | You might need vision then. |
| 18:48.43 | AchiestDragon | software is a diferent matter , although no time limit on how long it will take |
| 18:49.00 | VoodooZ_Work | that helps. |
| 18:49.19 | VoodooZ_Work | you might want to look into behaviour based methods. that's what I'm using. |
| 18:49.46 | AchiestDragon | vision well maybe , ultrasonic rainge finders , gps electronic compas ,and some environment mapping functions |
| 18:49.49 | VoodooZ_Work | Much more robust in a real world environment than your typical beginner's if-else-then/loop coding method. |
| 18:50.33 | AchiestDragon | vision in the form of video is deceptive , distance ranging can generate terain mapps a lot easyer |
| 18:50.40 | VoodooZ_Work | none of them are 100% reliable which makes it harder so the tough part is to integrate them together (sensor-fusion) |
| 18:51.25 | VoodooZ_Work | yeah, but they each have advantages. |
| 18:52.01 | AchiestDragon | well using a 200mhz arm micro , and upt to 4 cyclone 2 fpga boards doing hardware implimented functions |
| 18:52.16 | VoodooZ_Work | nice. |
| 18:52.39 | VoodooZ_Work | some of the vision stuff lends itself well to hardware implementation. |
| 18:53.36 | AchiestDragon | theres also wifi link to a remote system and the only plans for camara vision is just for remote monitoring of it |
| 18:56.25 | AchiestDragon | i have some good algorithoms for the motors and a sequencer that is adaptive to its environment |
| 18:57.14 | VoodooZ_Work | nice. homebrew or? |
| 18:57.39 | AchiestDragon | its a long term project for 2 reasons , 1 its going to take a long time to sort the software , and 2 i have to save up for the bits as i am going along |
| 18:57.51 | AchiestDragon | homebrew |
| 18:58.55 | VoodooZ_Work | I'd be interested in seeing some of your work. |
| 19:00.08 | AchiestDragon | http://www.whipy.demon.co.uk , part of the project , in that its the cnc machine i designed and built so i can make the parts for the robot |
| 19:00.42 | VoodooZ_Work | nice |
| 19:00.54 | VoodooZ_Work | mine is at http://robotics.no-ip.org |
| 19:02.17 | vmaster | ohh, nice, that cnc machine |
| 19:02.55 | *** join/#openjtag asdbigmac (n=asdbigma@85.216.68.31) |
| 19:03.37 | *** join/#openjtag velinp (n=velinp@c88-163.cable.netissat.bg) |
| 19:08.09 | ka6sox | back later.... |
| 19:16.57 | vmaster | I've started writing together what a generic JTAG interface could look like: http://openocd.berlios.de/web/?page_id=22 |
| 19:17.14 | vmaster | interface as in "supported functionality" |
| 19:17.41 | *** join/#openjtag Tiersten (n=tman@nslu2-linux/Tiersten) |
| 19:23.24 | AchiestDragon | ok silly question time , is that the site for this project ? |
| 19:24.15 | vmaster | mhh, no, that's the site for my project |
| 19:24.35 | AchiestDragon | k |
| 19:25.04 | AchiestDragon | well next silly question is there a site for this project yet |
| 19:25.33 | vmaster | openjtag.net |
| 19:26.01 | AchiestDragon | ty |
| 19:27.03 | AchiestDragon | maybe worth the site link beeing put in the chan topic |
| 19:35.40 | Tiersten | hmm |
| 19:35.47 | *** mode/#openjtag [+o Tiersten] by ChanServ |
| 19:35.56 | *** topic/#openjtag by Tiersten -> This is the place to discuss development of Open JTAG tools and Bootloaders - http://www.openjtag.net/ |
| 19:36.01 | *** mode/#openjtag [-o Tiersten] by Tiersten |
| 19:38.14 | AchiestDragon | k reading that site gives me a better idea of where the project is at |
| 19:39.09 | Tiersten | The wiki hasn't been updated lately sorry |
| 19:39.26 | AchiestDragon | np |
| 19:41.00 | AchiestDragon | although i would be tempted to use a fpga rather than a clpd , in that there is more future scope for the board then |
| 19:41.51 | AchiestDragon | and posibilaty of extra funtions , alternete configuration is posible with little effort |
| 19:45.36 | AchiestDragon | things like allowing software reconfiguration to allow for diferent jtag pinouts ( assuming the buffers used can support this also ) |
| 19:46.10 | AchiestDragon | would help where a non standard jtag pinout is used |
| 19:47.53 | AchiestDragon | it could also allow for it to be reconfigured to act as a isp unit (ok so diferent software ) but makes it more of a universal device |
| 19:49.29 | AchiestDragon | remembering that a hobbiest that uses jtag for testing and development programming , usualy has a need to do isp and maybe flash reprogramming , and i2c eprom reprogramming |
| 19:51.08 | AchiestDragon | allthough the software here is just for the jtag side if the unit has the capablilay its can be left for future implimentation or for others to write the other functions that may be posible from it |
| 19:53.29 | AchiestDragon | and the advantage that the one unit could be capable of more than a single function for verry little extra is a good point that i tink needs to be looked at even if its not imediatly going to include software support |
| 19:56.34 | AchiestDragon | has the dongle been built yet , is the design set or still in flux ? |
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| 20:28.43 | ka6sox | AchiestDragon, the interface looks good to me...we are working on the software and a FPGA board for allowing additional functionality |
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