irclog2html for #openjtag on 20051218

`01:03.59`	`*** join/#openjtag vmaster_ (i=vmaster@p549B5FCA.dip.t-dialin.net)`
`14:19.50`	`*** join/#openjtag bullet (n=bullet@143.29.78.83.cust.bluewin.ch)`
`14:25.39`	`lennert`	`there's no way to have xst infer a DDR MUX, right?`
`14:25.46`	`lennert`	`at least, i can't seem to get it to do that`
`14:30.14`	`vmaster_`	`heh, guess you're the only one in this channel who would know what to do with a DDR MUX ;)`
`14:32.24`	`lennert`	`hmm :)`
`15:08.31`	`*** join/#openjtag ulf_k (n=ulf_kypk@p54BDA9C8.dip0.t-ipconnect.de)`
`15:38.32`	`*** join/#openjtag prpplague (n=billybob@72.22.141.111)`
`15:57.31`	`lennert`	`btw, in case anyone reads the hoplite JBits tutorial, the diagrams are wrong in places`
`15:57.57`	`lennert`	`caveat lector`
`16:05.05`	`[g2]`	`lennert R0X0Rz`
`16:05.12`	`[g2]`	`congrats btw`
`16:05.49`	`[g2]`	`lennert so you're looking to do IP routing witn FPGAs for speed ?`
`16:22.10`	`lennert`	`hehe`
`16:22.22`	`lennert`	`well, that's one thing i would eventually like to look into`
`16:22.36`	`lennert`	`not for speed but just for fun`
`16:23.11`	`lennert`	`it's quick enough on the ixp`
`16:24.45`	`[g2]`	`the routing is not quick enough on the ixp ? don't the 2350s run faster ?`
`16:25.15`	`[g2]`	`A CAM chip is the answer for routing table lookups right ?`
`16:25.30`	`lennert`	`the routing _is_ quick enough on the ixps`
`16:25.48`	`lennert`	`you can pipeline memory references so you can do pretty crazy stuff and still get wire speed performance`
`16:25.48`	`[g2]`	`ah`
`16:26.23`	`lennert`	`i don't see the point of doing it in an fpga (which just complicates things) apart from making things hard on yourself (and at times i like to make things hard on myself)`
`16:27.30`	`[g2]`	`we did ingress and partial egress in FPGA several years ago`
`16:28.03`	`[g2]`	`we had about a dozen high-end FPGA guys and I was the lone NP guys with the Vitesse`
`16:28.42`	`lennert`	`there's an fpga between the gige interfaces and the ixp2400 on the radisys enp2611 board, and you can use it for some processing, but to do everything in the fpga seems a bit of a bad idea especially since the ixps are relatively cheap`
`16:29.08`	`[g2]`	`well this was 5+ years ago`
`16:29.26`	`lennert`	`admittedly, xilinx's high-end fpgas (the ones that cost $12k) have a bit more high-speed transceivers than the ixps do`
`16:29.38`	`[g2]`	`We had multipel GigE in the chassis and supported 1Million subs`
`16:32.02`	`lennert`	`at what company was that?`
`16:32.33`	`[g2]`	`a startup they spend 60M over several years`
`16:32.44`	`lennert`	`any product? :)`
`16:32.51`	`[g2]`	`product was all done and ready`
`16:32.58`	`[g2]`	`no market :(`
`16:33.06`	`lennert`	`ah`
`16:33.14`	`[g2]`	`3G never really arrived`
`16:33.16`	`lennert`	`"it's the market's fault!" :)`
`16:33.22`	`lennert`	`"3G" ?`
`16:33.31`	`lennert`	`you mean, as in UMTS/W-CDMA 3G?`
`16:33.31`	`[g2]`	`3G wireless`
`16:33.34`	`[g2]`	`nod`
`16:33.34`	`lennert`	`right`
`16:33.38`	`lennert`	`well`
`16:33.41`	`lennert`	`it's slowly arriving now :)`
`16:33.56`	`[g2]`	`it's been slowly arriving for years :)`
`16:34.42`	`lennert`	`GSM protocols are really baroque`
`16:34.48`	`[g2]`	`heh`
`16:35.36`	`lennert`	`another project i've been thinking about is a GSM jammer :)`
`16:36.13`	`[g2]`	`I think ppl already sell them.. for theaters etc.`
`16:36.23`	`lennert`	`yeah, i mean, not as a commercial product`
`16:36.33`	`lennert`	`as a kind of hobby thing`
`16:36.37`	`[g2]`	`Ah....`
`16:36.47`	`[g2]`	`I'd go for the SDR`
`16:36.56`	`[g2]`	`then you could handle it all :)`
`16:37.07`	`[g2]`	`the _soft_ BTS or whatever`
`16:37.08`	`lennert`	`yeah`
`16:37.15`	`lennert`	`software defined radio`
`16:37.24`	`lennert`	`base transceiver station? :)`
`16:37.29`	`[g2]`	`that's something the FPGA would be helpful with`
`16:37.34`	`[g2]`	`yeah`
`16:37.37`	`lennert`	`just generate white noise and mix it with the appropriate carrier`
`16:37.41`	`lennert`	`indeed`
`16:37.59`	`lennert`	`and surprise surprise, my virtex board has a triple 150MSPS 8bit D/A converter`
`16:38.21`	`lennert`	`it's really a VGA DAC, but you don't have to use it for VGA, eh? :)`
`16:38.32`	`lennert`	`3x75MHz of bandwidth is plenty`
`16:39.11`	`lennert`	`the problem is only that i'm generating ideas faster than i can implement them.. :)`
`16:39.22`	`[g2]`	`welcome to the club :)`
`16:39.58`	`[g2]`	`so is the DDR interface on the Big Vertex board or can the S3 do that too ?`
`16:40.20`	`[g2]`	`S3e maybe ?`
`16:41.37`	`lennert`	`the s3 also has ddr`
`16:42.02`	`lennert`	`i need the ddr mux for accessing the dual set of flipflops in every IOB`
`16:42.18`	`lennert`	`(each iob has two {input,output,tristate} flipflops, where the second set is only used for ddr)`
`16:42.42`	`[g2]`	`is that the on chip Block RAM ?`
`16:42.49`	`lennert`	`nope`
`16:42.50`	`[g2]`	`not off chip DDR memory`
`16:42.53`	`lennert`	`IOB = input/output block`
`16:43.05`	`lennert`	`the bits of logic that connect the pins to the logic inside the chip`
`16:43.16`	`[g2]`	`right`
`16:43.27`	`lennert`	`check out the sp3 datasheet (ds099.pdf) page 9`
`16:43.40`	`lennert`	`that sort-of shows the IOB structure (but is incomplete)`
`16:45.23`	`lennert`	`the hoplite JBits tutorial has a floorplan on p18 but that one's incorrect, even`
`16:50.09`	`[g2]`	`so one can actually to DDR memory terminations with S3 ?`
`16:50.31`	`[g2]`	`I guess the DCI help with terminations`
`16:50.53`	`lennert`	`you can hook an s3 up to ddr ram, yeah`
`16:51.01`	`lennert`	`what signaling do they use again.. sstl?`
`16:51.21`	`[g2]`	`dunno`
`16:51.44`	`[g2]`	`so many signalling types (and so many protocols) and so little time :)`
`16:51.49`	`lennert`	`yeah :)`
`16:52.31`	`lennert`	`the way the signaling standards are mapped into bits makes no sense at all`
`16:53.27`	`lennert`	`some signaling standard choices produce identical .bit files, too`
`16:53.37`	`[g2]`	`I think it's half history from the evolution of product lines and half Enlightenment`
`16:54.00`	`lennert`	`LVTTL 2mA and LVCMOS33 2mA produce the exact same bit pattern, by the way`
`16:54.05`	`lennert`	`s/by the way/for example/`
`16:54.17`	`lennert`	`so if you have a .bit file, you can't be 100% sure what signaling standards have been used`
`16:54.28`	`lennert`	`LVCMOS25 6mA is identical to LVCMOS33 8mA`
`16:54.52`	`lennert`	`LVTTL 4mA and LVCMOS33 4mA are identical`
`16:54.52`	`lennert`	`etc`
`16:55.18`	`lennert`	`i think the bit patterns control individual transistors`
`16:55.41`	`lennert`	`but i can't really guess how they are connected just from the bit patterns`
`16:56.10`	`lennert`	`dci is another mystery for now`
`16:57.11`	`[g2]`	`yeah I've got tons to learn in the EE dept. too`
`16:57.21`	`lennert`	`http://svn.wantstofly.org/vhdl/utils/decode_bit.c dumps .bit files in hex format, frame-by-frame`
`16:57.26`	`lennert`	`[g2]: yeah... :-/`
`16:59.56`	`[g2]`	`lennert the other day you suggested just writing to the GPIO register in a big loop to measure the timing right ?`
`17:00.01`	`lennert`	`yeah`
`17:00.09`	`lennert`	`i found the datasheet for the southbridge on my via epia board`
`17:00.13`	`lennert`	`(which has 8 exposed GPIOs)`
`17:00.27`	`lennert`	`i still have to look into that though`
`17:00.39`	`[g2]`	`I wanted to try the same thing on the Loft`
`17:00.54`	`lennert`	`okay`
`17:01.00`	`[g2]`	`I'll have to dig up the assembler instructions`
`17:01.03`	`lennert`	`so you want me to write the loop so that you can run it? :)`
`17:01.12`	`lennert`	`you don't really have to do it in assembler`
`17:01.33`	`lennert`	`let me hack that up`
`17:02.22`	`[g2]`	`C8004000 is the address of the GPIOs`
`17:02.44`	`lennert`	`yeah`
`17:02.50`	`lennert`	`IXP4XX_GPIO_GPOUTR is at offset 0x00 from that`
`17:03.08`	`[g2]`	`page 395 in the ixp42x Dev manual`
`17:03.22`	`lennert`	`or include/asm/arch-ixp4xx/ixp4xx-regs.h :D`
`17:05.55`	`lennert`	`ok, this should work`
`17:07.19`	`lennert`	`http://www.wantstofly.org/~buytenh/ixp4xx_gpio_twiddle.c`
`17:07.49`	`lennert`	`i've commented out the for-loop`
`17:08.19`	`lennert`	`can you run that to see if it gives sane results?`
`17:09.13`	`[g2]`	`sure`
`17:10.24`	`[g2]`	`we really want to be reading from 0xc8004008 though`
`17:10.33`	`[g2]`	`0 offset is for the config`
`17:11.22`	`[g2]`	`gpio[2]`
`17:11.33`	`lennert`	`offset 0x00 is IXP4XX_GPIO_GPOUTR`
`17:11.38`	`lennert`	`and gpio_line_set writes to IXP4XX_GPIO_GPOUTR`
`17:12.06`	`lennert`	`offset 0x08 is the input register, it says here`
`17:12.07`	`[g2]`	`right and that sets up whether the pins are Input/Tristate or Output`
`17:12.25`	`[g2]`	`right and 0x8 are the input values`
`17:12.28`	`lennert`	`no, that's gpio_line_config`
`17:12.44`	`lennert`	`input/output is set by IXP4XX_GPIO_GPOER, which is at offset 0x04`
`17:12.52`	`lennert`	`either that or the linux defines are all wrong :)`
`17:13.31`	`[g2]`	`right`
`17:13.38`	`[g2]`	`0x0 is the output`
`17:13.47`	`[g2]`	`0x4 is the output enbale`
`17:13.53`	`[g2]`	`0x8 is the input values`
`17:13.56`	`lennert`	`yeah`
`17:14.11`	`[g2]`	`so your code is correct for writing output`
`17:14.12`	`lennert`	`confusing intel docs, i bet`
`17:14.17`	`lennert`	`yeah`
`17:14.23`	`[g2]`	`but you are reading`
`17:14.29`	`lennert`	`i read it once`
`17:14.34`	`[g2]`	`nod`
`17:14.39`	`lennert`	`and then write it a million times`
`17:14.47`	`lennert`	`i read it because i want to make sure i don't fsck up the machine :)`
`17:15.01`	`lennert`	`it's allowed to read from the output register, no?`
`17:15.11`	`[g2]`	`nod`
`17:15.14`	`lennert`	`(it doesn't say in the header file)`
`17:15.25`	`lennert`	`okay`
`17:15.27`	`lennert`	`so so so`
`17:15.31`	`lennert`	`how fast is it? :)`
`17:15.39`	`[g2]`	`but we want to just write a value that drives the lower pins`
`17:15.54`	`lennert`	`well, for a timing test it doesn't matter what you write, does it?`
`17:16.12`	`lennert`	`if you have a 'scope you can toggle a gpio and check the frequency`
`17:16.15`	`[g2]`	`yeah as it will drive some of those lines`
`17:16.32`	`lennert`	`but how many cycles the gpio write takes doesn't depend on what you write`
`17:16.48`	`[g2]`	`no but I'm saying the hw may be unhappy`
`17:16.50`	`lennert`	`the bulk (99.999%) of the overhead is getting the write to the other side of the chip`
`17:16.56`	`lennert`	`well`
`17:17.09`	`lennert`	`we're only writing what was already there, don't we?`
`17:17.21`	`lennert`	`and if a gpio if configured as input, writing to the output register shouldn't change that?`
`17:17.42`	`[g2]`	`Ok... that's fair....`
`17:17.56`	`lennert`	`the ixp4xx doesn't have a "write a 1 to clear" or "write 1 to set" register.. else i would have used that and written just zeroes to it`
`17:20.33`	`lennert`	`so so so`
`17:20.35`	`lennert`	`how fast is it? :)`
`17:20.52`	`lennert`	`(or did it blow up?)`
`17:22.01`	`[g2]`	`setting up now`
`17:31.30`	`[g2]`	`booting almost there :)`
`17:31.47`	`lennert`	`:)`
`17:32.36`	`[g2]`	`I've been playing with bootp`
`17:32.44`	`[g2]`	`and the current setup is for that`
`17:33.36`	`[g2]`	`Ok it runs`
`17:34.12`	`*** join/#openjtag Trou (n=trou@tor/session/x-6bfc7b60de639896)`
`17:35.53`	`[g2]`	`Ok`
`17:36.52`	`lennert`	`so so so`
`17:36.52`	`[g2]`	`.05s for the 1M version`
`17:36.54`	`lennert`	`how fast is it? :)`
`17:37.06`	`lennert`	`how fast is the CPU?`
`17:37.11`	`[g2]`	`533`
`17:37.24`	`lennert`	`that's kind of impossibly fast`
`17:37.28`	`lennert`	`can you make it 16M ?`
`17:37.29`	`[g2]`	`it takes .01 for the program`
`17:37.35`	`[g2]`	`sure`
`17:37.56`	`lennert`	`you're sure you uncommented the for-loop? :)`
`17:37.58`	`lennert`	`try 16777216`
`17:38.34`	`[g2]`	`I did 16* that number`
`17:38.38`	`[g2]`	`literally 16*`
`17:38.40`	`lennert`	`that'll work`
`17:38.43`	`lennert`	`16*1048576 = 16777216`
`17:39.06`	`[g2]`	`I'm sure the compiler optimized it out :) preprocessor anyway`
`17:39.12`	`lennert`	`well, no`
`17:39.16`	`lennert`	`cause it's a volatile pointer`
`17:39.21`	`lennert`	`it's not allowed to optimise it away`
`17:39.31`	`[g2]`	`I meant the 16*`
`17:39.36`	`lennert`	`oooh, yeah`
`17:39.37`	`lennert`	`yeah, sure :)`
`17:39.51`	`[g2]`	`.760s`
`17:39.54`	`lennert`	`compiler will do that for you`
`17:40.08`	`lennert`	`hmmm`
`17:40.21`	`lennert`	`can you try 1024M loops?`
`17:40.33`	`[g2]`	`easy peasy :)`
`17:40.35`	`lennert`	`(1024*1048576 = 1073741824)`
`17:41.04`	`lennert`	`if the 0.760s figure is accurate, you can bitbang the gpios at 10MHz`
`17:41.15`	`Trou`	`hi guys, i'm looking for EJTAG v2.0 spec, does anyone have them ?`
`17:41.29`	`lennert`	`after that, try doing 16M reads in a loop (instead of writes)`
`17:41.32`	`lennert`	`Trou: sorry, nope`
`17:41.51`	`[g2]`	`I don't have one but the #openwrt guys play with EJTAG`
`17:42.04`	`Trou`	`yup, already asked there`
`17:42.19`	`Trou`	`looks like noone has them :(`
`17:42.39`	`[g2]`	`there were a couple guys doing EJTAG`
`17:42.45`	`[g2]`	`I'm not sure who`
`17:42.51`	`Trou`	`yeah, lightbulb mainly`
`17:43.09`	`[g2]`	`and some software are written up on the sveasoft forum`
`17:43.09`	`Trou`	`but he wasn't seen there since almost a month and doesn't answer to mails :x`
`17:43.26`	`[g2]`	`yeah lightbulb was doing that a year+ ago`
`17:43.30`	`vmaster`	`key2 talked a lot about ejtag`
`17:43.31`	`Trou`	`ah ?`
`17:43.40`	`Trou`	`i'm going to check the sveasoft forum`
`17:43.47`	`vmaster`	`isn't the ejtag specs available from mips?`
`17:43.57`	`[g2]`	`48.390s for 1024M`
`17:43.59`	`Trou`	`it is, but only v 3.10`
`17:44.06`	`Trou`	`i found 2.60 on google but no 2.0`
`17:44.33`	`lennert`	`[g2]: ok, so you can bitbang at about 11MHz`
`17:44.45`	`lennert`	`[g2]: can you try reads now?`
`17:44.59`	`vmaster`	`try two writes and one read`
`17:45.10`	`[g2]`	`sure x = gpio[2] ?`
`17:45.22`	`lennert`	`[g2]: for example`
`17:47.03`	`Trou`	`no luck on sveasoft, thanks anyway :)`
`17:47.07`	`*** part/#openjtag Trou (n=trou@tor/session/x-6bfc7b60de639896)`
`17:48.11`	`[g2]`	`reads appear to be way slower or there's an error`
`17:48.18`	`lennert`	`reads _are_ way slower`
`17:48.25`	`lennert`	`20x, easily`
`17:48.37`	`lennert`	`since the chip stalls on them`
`17:49.08`	`[g2]`	`so then the writes problaby don't really run at that rate then`
`17:49.32`	`lennert`	`they do..`
`17:49.55`	`lennert`	`i'm pretty sure you'll see a 11MHz square wave if you toggle one of the gpios`
`17:49.56`	`[g2]`	`2m25.160s`
`17:50.12`	`lennert`	`[g2]: for 16M reads? or 16M (write+write+read)s ?`
`17:50.19`	`[g2]`	`1024M`
`17:50.30`	`lennert`	`1024M reads or 1024M (write+write+reads)s ?`
`17:50.43`	`[g2]`	`just read`
`17:50.50`	`[g2]`	`x = gpio[2]`
`17:50.56`	`lennert`	`ok`
`17:51.02`	`lennert`	`7396953 per second`
`17:51.22`	`lennert`	`so reads are 72 cycles each and writes are 26 cycles each`
`17:51.31`	`lennert`	`still pretty good`
`17:51.50`	`lennert`	`so write+write+read is 124 cycles`
`17:51.55`	`[g2]`	`well if we can really drive at 11M that's ok for programming :)`
`17:52.03`	`lennert`	`4.2MHz if you are shifting something out`
`17:52.13`	`lennert`	`and 10.25MHz if you're not shifting anything out`
`17:52.23`	`lennert`	`give or take`
`17:52.27`	`lennert`	`not bad at all`
`17:54.51`	`[g2]`	`THX`
`17:54.58`	`[g2]`	`for the program`
`17:55.05`	`[g2]`	`and the help :)`
`17:55.07`	`lennert`	`np`
`17:55.20`	`[g2]`	`I've got 5 GPIOs on the Loft`
`17:55.25`	`lennert`	`now it's up to you to hack up a jtag daughterboard :)`
`17:55.42`	`[g2]`	`I don't need one`
`17:55.52`	`[g2]`	`It's 5 or 6 wires`
`17:56.00`	`lennert`	`yeah`
`17:56.07`	`[g2]`	`plus tying the ground together`
`17:56.15`	`lennert`	`are they at the right level though?`
`17:56.21`	`lennert`	`(what level is jtag, anyway?)`
`17:56.25`	`lennert`	`(3.3? 2.5?)`
`17:56.31`	`[g2]`	`I think it's 3.3`
`17:56.35`	`[g2]`	`I'll have to check`
`17:56.54`	`[g2]`	`but I should be able to have one Loft JTAG another`
`17:57.09`	`[g2]`	`if I've got enogh pins with 5`
`17:58.12`	`lennert`	`TCK, TMS, IN, OUT and maybe TRST`
`17:58.48`	`lennert`	`s/IN/TDI/;s/OUT/TDO/ of course`
`17:58.58`	`[g2]`	`of course :)`
`17:59.39`	`[g2]`	`I could probably cut the SCL line for the I2C chips and pick up 2 more (SDA and SCL) if need bot`
`17:59.41`	`[g2]`	`s/bot/be/`
`18:00.01`	`lennert`	`5 should be enough`
`18:00.14`	`[g2]`	`that's sweet`
`18:01.01`	`[g2]`	`I've to a 6 pin flying lead from DigilentInc that plugs onto the board header for $4.95`
`18:01.20`	`[g2]`	`all 5 pins are GPIO 0-4`
`18:01.56`	`[g2]`	`well wonderful news and great work`
`18:02.12`	`[g2]`	`I've got to get lunch (the family is eating)`
`18:02.18`	`[g2]`	`THX again`
`18:02.23`	`lennert`	`have a nice meal`
`18:02.27`	`lennert`	`talk to you when you get back :)`
`18:12.02`	`vmaster`	`using a 533mhz cpu to do jtag bitbanging is _cruel_ ;)`
`18:13.24`	`vmaster`	`a 60mhz lpc (arm7) is faster - 2 cycles per read or write`
`18:14.34`	`lennert`	`GPIOs are integrated into the main datapath?`
`18:18.05`	`lennert`	`yeah, it's a bit of a rude solution :)`
`18:19.29`	`[g2]`	`vmaster the lpc (Philips) run @ 60Mhz and can do GPIO in 2 instructions ?`
`18:20.14`	`vmaster`	`yes, the lpcs run at 60mhz and do one gpio access every two cycles`
`18:20.29`	`vmaster`	`i measured 15mhz when toggling one bit`
`18:20.32`	`[g2]`	`how many GPIOs are there`
`18:20.36`	`vmaster`	`dozens`
`18:20.50`	`vmaster`	`depending on the chip and package`
`18:20.51`	`[g2]`	`what do they cost ?`
`18:20.57`	`[g2]`	`any URLs ?`
`18:21.07`	`vmaster`	`olimex has a lot of lpc boards`
`18:21.11`	`vmaster`	`olimex.com`
`18:21.29`	`vmaster`	`there's even one with a usb 2.0 device port, iirc`
`18:23.43`	`vmaster`	`what i don't know is how much help the usb device port requires from the processor, like servicing interrupts and so on`
`18:24.08`	`[g2]`	`thx`
`18:24.11`	`[g2]`	`bbiab`
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`18:30.22`	`vmaster`	`A device with a very versatile synchronous serial interface would be nice - something that would allow you offload the serializing - it's just 'expensive' doing that in software`
`18:30.29`	`vmaster`	`*to`
`18:30.59`	`vmaster`	`motorola/freescale have SSIs capable of what JTAG needs, iirc`
`18:31.07`	`vmaster`	`the bdi uses one of these`
`18:31.25`	`lennert`	`the Abba-tron? :)`
`18:31.36`	`vmaster`	`yep`
`18:52.24`	`vmaster`	`mhh... the SSC on Atmel's SAM chips should work, but they have no high-speed peripherals, only full-speed`
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