irclog2html for #openjtag on 20051207

`00:11.57`	`*** join/#openjtag vmaster_ (i=vmaster@p549B3DDE.dip.t-dialin.net)`
`01:26.22`	`*** join/#openjtag ka6sox (n=ka6sox@nslu2-linux/ka6sox)`
`02:26.38`	`*** join/#openjtag ByronT (i=byron-po@nslu2-linux/ByronT)`
`05:07.22`	`*** join/#openjtag ByronT (n=byron-po@nslu2-linux/ByronT)`
`09:08.47`	`*** join/#openjtag ep1220 (n=NN@gate.epatec.at)`
`12:35.04`	`*** join/#openjtag bullet (n=bullet@159.17.78.83.cust.bluewin.ch)`
`12:55.31`	`[g2]`	`ep1220 png`
`12:55.46`	`ep1220`	`[g2]: morning`
`12:55.53`	`[g2]`	`yes it is :)`
`12:56.17`	`[g2]`	`so the hardware boads are ready to go ?`
`12:56.21`	`[g2]`	`boards`
`12:56.27`	`ep1220`	`yes`
`12:56.55`	`[g2]`	`they do both serial and JTAG ?`
`12:57.05`	`ep1220`	`yes`
`12:57.30`	`[g2]`	`from Windows, Linux, both ?`
`12:57.46`	`ep1220`	`Windows: both no problem`
`12:57.59`	`ep1220`	`Linux: needs some tinkering to get both at the same time`
`12:58.19`	`ep1220`	`when the serial driver is installed it allocs both channels`
`12:58.30`	`ep1220`	`so the JTAG soft can not access`
`12:58.37`	`[g2]`	`this is all USB 1.1 stuff right ?`
`12:58.53`	`ep1220`	`full speed only`
`12:59.04`	`[g2]`	`12mbs`
`12:59.07`	`ep1220`	`EEPROM decides if the device detects as 1.1 or 2.0`
`12:59.25`	`[g2]`	`nod`
`12:59.29`	`ep1220`	`yes 12mb, on the JTAG theoretical max is 6Mbps`
`12:59.50`	`[g2]`	`I'm thinking about the logging speed of the USB transactions in Linux`
`13:00.01`	`[g2]`	`I think USB debug will dump them out`
`13:00.24`	`ep1220`	`logging speed ?`
`13:00.38`	`[g2]`	`so for debugging the driver I think we can capture all the transactions`
`13:00.46`	`[g2]`	`that makes for simple debugging`
`13:00.54`	`ep1220`	`on windows this was no problem`
`13:01.00`	`[g2]`	`possibly even play back`
`13:01.34`	`ep1220`	`i do not think there is much need for debugging at the USB packet level`
`13:02.15`	`ep1220`	`The serial + JTAG problem is more a VID/PID issue + what the driver uses.`
`13:02.41`	`ep1220`	`The EEPROM has fields to tell the OS which channel to use for serial and which for parallel/JTAG`
`13:02.52`	`ep1220`	`seems ftdisio does not care ...`
`13:03.40`	`ep1220`	`but that one is OS (iirc)`
`13:03.53`	`[g2]`	`Ok what are you planning on selling your board for ?`
`13:04.53`	`[g2]`	`to end users`
`13:05.15`	`ep1220`	`I can sell the PCB alone at 14EUR`
`13:05.29`	`[g2]`	`I'm looking for a JTAG solution for Loft users`
`13:05.38`	`ep1220`	`for complete boards I have not decided on an enduser price`
`13:05.41`	`[g2]`	`how big is it ?`
`13:05.50`	`ep1220`	`80 x100 mm`
`13:06.16`	`ep1220`	`divide by 25,4 to get inches`
`13:06.52`	`ep1220`	`if volume is OK, it might make a SMD only board`
`13:07.11`	`ep1220`	`s/it/I/`
`13:07.47`	`[g2]`	`well you've got the design right ?`
`13:07.53`	`ep1220`	`my reasoning. without software there will not be many customers ;-)`
`13:08.02`	`ep1220`	`so i made this kit first`
`13:08.03`	`[g2]`	`it'd just be a BOM and PCB change`
`13:08.34`	`ep1220`	`I must add the parts from the module to the PCB`
`13:08.53`	`ep1220`	`so it is not totally trivial`
`13:08.58`	`*** join/#openjtag prpplague (n=billybob@216.110.99.89)`
`13:09.13`	`ep1220`	`also can not be soldered by hand`
`13:09.46`	`bullet`	`well, it can, but you sure don't want to ;)`
`13:10.25`	`[g2]`	`it doesn't make much sense except for POC or debugging`
`13:10.36`	`ep1220`	`POC ?`
`13:10.43`	`[g2]`	`Proof-of-Concept`
`13:10.50`	`[g2]`	`sorry`
`13:10.57`	`ep1220`	`you mean te handsoldering ?`
`13:11.01`	`[g2]`	`yeah`
`13:11.11`	`[g2]`	`I was replying to bullet's comment`
`13:11.26`	`ep1220`	`in my experience one edns up debugging the soldering joints ;-)`
`13:11.31`	`ep1220`	`ends up`
`13:11.40`	`[g2]`	`:)`
`13:13.00`	`ep1220`	`If one commits to approx. 100 units, it is no problem to first get a few manufactured professionally to start with`
`13:17.02`	`prpplague`	`getting assembly for something with that level of complexity is pretty cheap and easy`
`13:17.46`	`[g2]`	`hey prpplague`
`13:18.09`	`ep1220`	`prpplague: we are talking about directly soldering the FTDI to a PCB, that one is 0.5 fine-pitch`
`13:18.13`	`ep1220`	`0.5mm`
`13:18.46`	`prpplague`	`yea, doing that by hand would be tricky to do with that kind of qty`
`13:19.03`	`prpplague`	`ep1220: could try using a toaster oven technique`
`13:19.05`	`vmaster_`	`regarding jtag and serial at the same time: linux > 2.6.13 allows you to unregister drivers from userland`
`13:19.24`	`vmaster_`	`so you just let ftdi_sio take both endpoints, and then unregister it from the jtag endpoint`
`13:20.25`	`[g2]`	`vmaster unregister the second endpoint so it could be used for serial ?`
`13:21.32`	`vmaster`	`mhh, well, if you want don't want to mess around with a vid/pid of your own you could just use ftdi's default. in that case, ftdi_sio would use both for serial, so you unregister ftdi_sio from the endpoint you want to use as jtag`
`13:22.02`	`vmaster`	`with linux 2.6.15 or possibly .16, it's going to be possible to assign drivers to vid/pid from userspace`
`13:22.53`	`[g2]`	`hotplug ?`
`13:23.08`	`vmaster`	`hotplugging uses the vid/pid entries from the driver`
`13:23.17`	`ep1220`	`another option: add code to ftdi_sio so it checks what the EEPROM says ..`
`13:23.23`	`ep1220`	`<PROTECTED>`
`13:23.38`	`vmaster`	`heh, yeah, good luck getting a change for your jtag interface upstream ;)`
`13:24.28`	`[g2]`	`if I understand you guys, the ftdi serial driver takes both channels and one would need to be unregistered to be used as JTAG`
`13:24.36`	`ep1220`	`nod`
`13:24.59`	`vmaster`	`but that only works with linux >= 2.6.13`
`13:24.59`	`ep1220`	`at the moment i unload the entire ftdi_sio module`
`13:26.36`	`[g2]`	`so are you guys more interested in this known working solution or a FPGA based one ?`
`13:27.29`	`vmaster`	`i couldn't get more than an effective tck rate of ~1mhz from the ft2232c`
`13:27.48`	`vmaster`	`so a fpga based solution is still on my list`
`13:28.17`	`vmaster`	`but for now, i'm happy with the ft2232c`
`13:28.32`	`[g2]`	`vmaster do you program verilog/vhdl ?`
`13:29.10`	`vmaster`	`heh, i tried it, but due to a lack of time didn't finish my initial design for the parallel port`
`13:29.33`	`[g2]`	`I've got a Black Dog that is cool`
`13:30.02`	`[g2]`	`I think it's got most everything we need on it except a MMC to JTAG Header converter`
`13:30.44`	`[g2]`	`They cost $199 for the 256MB flash and 64MB ram on board, run Debian Sarge in the PPC hardcore on the Xilinx inside`
`13:30.56`	`[g2]`	`and have USB 2.0`
`13:31.39`	`[g2]`	`So I'm weight cost/schedule against building ep1220's device, or getting devices for members here and just moving to something like that`
`13:32.30`	`[g2]`	`I've talked to the company that makes them and later in 2006 is may be possible to OEM them`
`13:33.19`	`[g2]`	`I think ep1220 has done tremendous work and is the leader of getting things done`
`13:33.24`	`[g2]`	`and working`
`13:33.58`	`ep1220`	`[g2): I want a JTAG with level-shifters and protected outputs`
`13:33.59`	`[g2]`	`I'm ready for JTAG and in a couple months my board users will be ready too`
`13:34.22`	`prpplague`	`"board users" ?`
`13:34.31`	`vmaster`	`those that buy his loft, i guess`
`13:34.32`	`[g2]`	`ep1220 a dongle can have that`
`13:34.35`	`ep1220`	`so would have to add a similar board like mine, except with an FPGA in place of the FTDI`
`13:34.41`	`[g2]`	`yes Loft's are shipping`
`13:35.02`	`ep1220`	`But then You pay 199$ for the USB IF.`
`13:35.21`	`vmaster`	`the blackdog seems a bit over-sized`
`13:35.26`	`ep1220`	`For that price You can an ARM + network module easily.`
`13:35.37`	`ep1220`	`yu can add`
`13:35.38`	`prpplague`	`[g2]: Loft ?`
`13:35.52`	`[g2]`	`ep1220 $199 is for the USB IF, a Hardcore, FPGA, Fingerprint scanner, dev kit ....`
`13:35.59`	`[g2]`	`yeah`
`13:36.04`	`[g2]`	`prpplague`
`13:36.18`	`[g2]`	`http://www.giantshoulderinc.com/hw-4533`
`13:36.21`	`vmaster`	`mhh, i wonder how they can sell the blackdog for so little money`
`13:36.40`	`[g2]`	`http://www.giantshoulderinc.com/ab3/case.jgp`
`13:36.45`	`[g2]`	`doh! that jpg`
`13:37.02`	`ep1220`	`[g2]: but what use is this other stuff in a JTAG IF ?`
`13:37.02`	`[g2]`	`vmaster $20 in venture funding`
`13:37.07`	`[g2]`	`$20M`
`13:37.33`	`[g2]`	`they are going after the enterprise market this is just reducing their development costs`
`13:37.48`	`bullet`	`[g2]: how much will your loft cost?`
`13:38.10`	`[g2]`	`dev kits are selling for $325 board and PS, and $349 with case`
`13:38.27`	`[g2]`	`that's a 533Mhz industrial temp board`
`13:38.56`	`bullet`	`ui, 4x mini-pci? quite a lot`
`13:39.08`	`[g2]`	`ui ?`
`13:39.12`	`prpplague`	`interesting board`
`13:39.21`	`[g2]`	`actually 3 miniPCI`
`13:39.23`	`bullet`	`ui! :) that's german for, wow`
`13:39.31`	`[g2]`	`:)`
`13:39.47`	`[g2]`	`you can also get a 4 MiniPCI no USB version`
`13:39.55`	`[g2]`	`it'll be a little cheaper`
`13:40.30`	`[g2]`	`bullet it also does passive POE and can handle 4 radio cards for full duplex dual channel wifi`
`13:40.39`	`[g2]`	`in multiple bands or not`
`13:40.44`	`[g2]`	`all run from the POE`
`13:41.00`	`bullet`	`nice nice`
`13:41.22`	`[g2]`	`I'm bringing up the Aetheros and IPW2200 cards now`
`13:45.14`	`[g2]`	`well trying anyway :)`
`14:26.04`	`prpplague`	`[g2]: since you have $20M can i borrow about $50? hehe`
`14:27.20`	`lennert`	`oooh.. we get to submit our wishlists to [g2] ? :)`
`14:29.00`	`prpplague`	`"dear santa, please bring me a 4 channel digital oscope, weller reflow over, and last but not least a bdi2000 , thanks, davey"`
`14:29.19`	`vmaster`	`mhh, the blackdog guys have the 20m, right?`
`14:30.57`	`lennert`	`i want a scope like that, a good fluke, a good lab power supply, a v2p board with gige, and a ton of other crap`
`14:43.37`	`prpplague`	`hehe, i've had the money for a good oscope a couple times, hehe, then i went to the nudie bar`
`14:43.47`	`lennert`	`hmmmmm :)`
`14:43.52`	`lennert`	`such a waste!`
`14:43.58`	`prpplague`	`hehe`
`14:45.01`	`lennert`	`i'm thinking about buying a heap of stuff for myself as 'investment'`
`14:47.21`	`prpplague`	`yea, me too`
`15:07.58`	`[g2]`	`prpplague I don't have $20M`
`15:08.15`	`[g2]`	`if I had $20M all you guys would have more hw than you'd know what to do with`
`15:08.51`	`[g2]`	`Realm Systems got like $20M in two rounds of VC financing (actually I think it's 17)`
`15:10.27`	`[g2]`	`You know we should just make an apdapter that plugs into the CF slot on the Loft`
`15:10.42`	`[g2]`	`then we could just drive stuff over the Expansion Bus`
`16:00.24`	`*** join/#openjtag prpplague^2 (n=billybob@72.22.129.170)`
`16:01.19`	`[g2]`	`lennert you've still got your S3 ?`
`16:54.13`	`ka6sox`	`Vulture Capitalists`
`18:00.26`	`prpplague`	`~seen beewoolie`
`18:00.31`	`purl`	`beewoolie <n=beewooli@florence.buici.com> was last seen on IRC in channel #openjtag, 69d 23h 55m 6s ago, saying: 'Right. I get that part. My block flashing code is way faster than the byte flashing.'.`
`18:00.40`	`prpplague`	`~seen beewoolie-afk`
`18:00.41`	`purl`	`beewoolie-afk <n=beewooli@206.124.142.26> was last seen on IRC in channel #openjtag, 14d 20h 28m 57s ago, saying: 'prpplague: I found the problem...'.`
`18:00.51`	`prpplague`	`~seen beewoolie-oncrack`
`18:00.52`	`purl`	`i haven't seen 'beewoolie-oncrack', prpplague`
`18:01.11`	`prpplague`	`feel lucky`
`18:12.49`	`*** join/#openjtag [hell]defekt (i=defekt@hell.cybcom.net)`
`18:14.04`	`*** join/#openjtag [hell]defekt (i=defekt@hell.cybcom.net)`
`18:23.07`	`*** join/#openjtag [hell]defekt (i=defekt@hell.cybcom.net)`
`18:24.04`	`lennert`	`[g2]: yeah, i still have my s3`
`18:24.18`	`lennert`	`prpplague: so you _have_ seen him on crack before?`
`18:24.37`	`prpplague`	`lennert: hehe`
`18:24.43`	`prpplague`	`lennert: no, just being silly`
`18:24.54`	`lennert`	`:)`
`18:25.52`	`*** join/#openjtag bullet (n=bullet@196.49.62.81.cust.bluewin.ch)`
`19:08.19`	`*** join/#openjtag ByronT-Away (i=byron-po@nslu2-linux/ByronT)`
`19:20.02`	`[g2]`	`ep1220 vmaster lennert are you guys interested in doing JTAG for the GESBC-9312-sx boards ?`
`19:20.12`	`[g2]`	`http://www.glomationinc.com`
`19:20.31`	`[g2]`	`I think I might have a sponsor that will support our efforts with hw`
`19:21.56`	`[g2]`	`ep1220 I think that board would work with your device and 20-pin arm`
`19:58.41`	`vmaster`	`[g2]: i already have a arm7/arm9 debugger that works with wigglers and ft2232c`
`19:58.51`	`vmaster`	`it just needs those finishing touches i never find time for`
`19:59.52`	`[g2]`	`vmaster Ok will the debugger work with ep1220 device ?`
`20:00.17`	`vmaster`	`yeah, all the logic is inside the ft2232c`
`20:02.11`	`[g2]`	`vmaster there's a usb driver and then some stuff on the ft2232c for the JTAG translation`
`20:05.38`	`lennert`	`[g2]: i'm always interested in more hardware =p`
`20:06.05`	`lennert`	`[g2]: this board actually looks pretty cool. do you have one of them, do you know what the max gpio clock frequency is?`
`20:07.59`	`[g2]`	`lennert dunno about the max gpio`
`20:08.10`	`[g2]`	`I know the chip family is the Cirrus 93xx`
`20:10.17`	`[g2]`	`lennert I don't have one but I will soon :)`
`20:10.56`	`lennert`	`okay`
`20:11.08`	`lennert`	`i'll send you a test proggy to try out what max clock rate you can get`
`20:12.57`	`[g2]`	`lennert how are you going to measure ?`
`20:13.09`	`[g2]`	`I think I've got a 200Mhz 9302 around somewhere`
`20:14.13`	`[g2]`	`or are your FPGA skillz so great that I can hookup a couple wires and just see the output on the VGA screeen ?`
`20:14.59`	`lennert`	`no, you just check how long an MMIO write takes`
`20:15.11`	`lennert`	`do a couple million in a loop`
`20:15.47`	`[g2]`	`ok, you're saying that the CPU will stall on the write and you know the timing`
`20:15.50`	`lennert`	`btw, writing a frequency counter for the sp3 with vga output wouldn't even be all that hard, i think...`
`20:15.59`	`lennert`	`indeed, if you do the mapping uncached`
`20:16.21`	`lennert`	`once the 'gpio unit' (or whatever unit it is) has received the write, it'll toggle the gpio pretty quickly`
`20:16.30`	`lennert`	`it's the path to the 'gpio unit' that takes the most time`
`20:16.31`	`[g2]`	`lennert that wasn't a total joke`
`20:16.59`	`lennert`	`the frequency counter, you mean? in fact, i think i can whip one up pretty quickly ;)`
`20:17.33`	`[g2]`	`can you do colored DIOs too ?`
`20:17.41`	`lennert`	`DIO ?`
`20:17.46`	`[g2]`	`Digital I/O`
`20:17.52`	`lennert`	`how do you mean, colored?`
`20:18.06`	`[g2]`	`Green = 0, Red = 1, Yellow = float`
`20:18.25`	`lennert`	`i'm not sure whether you can detect high-impedance state`
`20:18.52`	`[g2]`	`it'd probably be a driven line`
`20:18.55`	`lennert`	`you _could_ partial reconfig the fpga 20 times a second to toggle between pullup and pulldown, and then detect a 10Hz square wave as high impedance..`
`20:19.15`	`lennert`	`but that has issues of itself :)`
`20:19.30`	`[g2]`	`no, I'm thinking simple feed back for GPIOs`
`20:20.01`	`lennert`	`making a simple vga output saying which line is high and which is low, that should be not very hard`
`20:20.10`	`[g2]`	`I know`
`20:20.32`	`[g2]`	`not for the FPGA Master :)`
`20:20.46`	`lennert`	`[g2]: how's your vhdl foo, then?`
`20:21.00`	`[g2]`	`non-existant`
`20:21.07`	`lennert`	`any plans?`
`20:21.29`	`lennert`	`or ambitions?`
`20:21.46`	`[g2]`	`I've had plans for a couple years but kernel hacking, toolchains, board building etc has gotten in the way`
`20:21.54`	`lennert`	`i see..`
`20:21.58`	`lennert`	`yeah, too many plans, i know that..`
`20:22.07`	`[g2]`	`I've followed the uBlaze ML for the last couple years`
`20:22.19`	`lennert`	`oh`
`20:22.24`	`[g2]`	`but now Hardcores are relatively cheap`
`20:22.31`	`lennert`	`any posts from a guy @liacs.nl ? he's a nut.`
`20:22.41`	`[g2]`	`i.e. blackdog`
`20:23.11`	`lennert`	`blackdog is $199, right?`
`20:23.15`	`[g2]`	`yeah`
`20:23.29`	`lennert`	`so what does it have, again? sdram?`
`20:23.42`	`vmaster`	`lennert: why is the gpio frequency important for you?`
`20:23.50`	`vmaster`	`philips lpc's are nice in that regard`
`20:23.53`	`[g2]`	`64MB SDRAM, 256MB flash, PPC, MMC slot, fingerprint scanner`
`20:24.01`	`[g2]`	`hardcore`
`20:24.04`	`[g2]`	`runs sarge`
`20:24.14`	`lennert`	`all vhdl available?`
`20:24.18`	`[g2]`	`yeah`
`20:24.21`	`[g2]`	`well most`
`20:24.33`	`[g2]`	`I haven't really looked at the package`
`20:24.54`	`[g2]`	`they have that 50K grand prize`
`20:39.33`	`*** join/#openjtag ByronT-Away (i=byron-po@nslu2-linux/ByronT)`
`20:41.28`	`*** join/#openjtag [hell]defekt (i=defekt@hell.cybcom.net)`
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`23:50.27`	`[g2]`	`vmaster around ?`

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