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| 17:26.52 | lennert | ka6sox: around? |
| 17:27.20 | ka6sox | no...I'm square |
| 17:27.33 | lennert | :) |
| 17:27.41 | ka6sox | g'day lenner |
| 17:27.43 | ka6sox | t |
| 17:27.45 | ka6sox | wazzup? |
| 17:27.46 | lennert | good day ka6sox |
| 17:27.49 | lennert | vhdl trouble :) |
| 17:27.56 | lennert | or actually, the vhdl is okay |
| 17:28.10 | ka6sox | but.... |
| 17:28.28 | lennert | i made an uart |
| 17:28.38 | lennert | and i hook up the uart so that it loops back data from the pc back to the pc |
| 17:29.02 | lennert | ..but it loses every 660th character :D |
| 17:29.28 | lennert | my pc is probably using a slightly faster 1.8432MHz clock than my spartan3 board is, right? |
| 17:30.30 | ka6sox | Its usually a case of not staying in the middle of the sampling cycle. |
| 17:30.46 | ka6sox | what is your oversample rate? |
| 17:30.48 | lennert | (sorry, 554th. a 553-byte burst comes back as 553, a 554-byte burst comes back as 553 bytes.) |
| 17:30.51 | lennert | ka6sox: 16 |
| 17:31.03 | lennert | sample at 7th bit time |
| 17:31.17 | ka6sox | you aren't looking for an edge? |
| 17:31.22 | lennert | i do |
| 17:31.32 | lennert | maybe you want to have a look at the vhdl? |
| 17:31.37 | ka6sox | url to code? |
| 17:31.39 | lennert | http://svn.wantstofly.org/vhdl/uart/ |
| 17:32.07 | lennert | i _think_ i have the sampling okay |
| 17:32.14 | lennert | but i didn't fully walk it through yet |
| 17:32.22 | lennert | 'uart' |
| 17:32.37 | lennert | i'm not seeing any framing errors |
| 17:33.09 | lennert | in the receiver i have a check "has the receive register been emptied yet?", and i see that trigger |
| 17:33.31 | lennert | the rx filter is a simple 2-bit up/down counter for filtering out single-bit errors |
| 17:34.42 | lennert | (i added http://www.wantstofly.org/~buytenh/overrun-framing and i see 'overrun' toggle every 554th byte) |
| 17:36.27 | ka6sox | lemme look at that. |
| 17:38.18 | lennert | (the interface is clockless: the receiver toggles 'request' when a byte has been received, and whenever is connected to the receiver is supposed to toggle 'acknowledge' when it has received the byte) |
| 17:47.49 | lennert | ka6sox: if i tell the transmitter to make the start bit 15 bit times long instead of 16 bit times long, i receive all characters.. |
| 17:48.51 | ka6sox | then it *is* a framing error.... |
| 17:49.05 | lennert | ? |
| 17:49.21 | lennert | i'm merely speeding up the transmitter |
| 17:49.29 | lennert | i have pc -> sp3 receiver -> sp3 transmitter -> pc |
| 17:49.31 | ka6sox | wait... |
| 17:49.42 | lennert | the sp3 receiver -> sp3 transmitter is where characters get lost (i assume) |
| 17:49.44 | ka6sox | is this in your TX code or RX code? |
| 17:50.10 | lennert | i'm speeding up the sp3 transmitter by making each byte 1 bit time shorter |
| 17:50.26 | lennert | ka6sox: this hack, in the tx code |
| 17:52.06 | ka6sox | so its 15bit times long instead of 16bit times long. |
| 17:52.17 | lennert | the start bit, yes |
| 17:52.28 | lennert | overall, the transmitted byte is 159 bit times long |
| 17:52.38 | lennert | and i don't lose characters anymore |
| 17:52.39 | ka6sox | just the start bit...okay drawing the timing diagram. |
| 17:52.52 | lennert | if i make the transmitted byte 160 bit times long, i do lose every 554th character |
| 17:53.04 | ka6sox | this would go away if you made a small fifo |
| 17:53.33 | lennert | i think the pc's 1.8432MHz is 1 in 90000 parts faster than the sp3 1.8432MHz |
| 17:53.40 | ka6sox | yep |
| 17:53.41 | lennert | so i think if i made a fifo it would also overflow |
| 17:53.51 | lennert | (because i'm just flooding it with characters) |
| 17:54.22 | lennert | (specifically, i'm looping vmlinuz through it :) |
| 17:54.24 | ka6sox | the worst case scenario is 3 bytes |
| 17:54.48 | lennert | the sp3 board doesn't have the hw flow control signals hooked up :-/ |
| 17:54.49 | ka6sox | mostly you would see the buffer only get 2 deep. |
| 17:55.37 | lennert | ok, let me try that |
| 17:55.39 | ka6sox | when the stop bit is received you transfer the data to the fifo. |
| 17:55.54 | lennert | that's kind-of what i do now |
| 17:56.04 | lennert | i check if the stop bit is 1, otherwise i flag a framing error |
| 17:56.16 | ka6sox | but you need to implement the fifo eles you get an overrun. |
| 17:56.30 | ka6sox | er else |
| 17:56.39 | lennert | well |
| 17:56.52 | lennert | if the pc transmits faster than the sp3, i'll always get overruns, right? |
| 17:56.59 | ka6sox | yesw |
| 17:57.11 | ka6sox | it will shift the problem out further but yes. |
| 17:57.21 | lennert | okay |
| 17:57.23 | lennert | thanks for your help |
| 17:57.33 | lennert | other than this, the serial rx/tx is working pretty nicely |
| 17:57.44 | ka6sox | loopback is the worst case |
| 17:57.50 | lennert | yeah |
| 17:58.02 | ka6sox | so any other usage would be much faster. |
| 17:58.04 | lennert | whee |
| 17:58.05 | lennert | f9e4fe4bc084953815650726c30e053a /boot/vmlinuz-2.6.13-1.1526_FC4smp |
| 17:58.05 | lennert | f9e4fe4bc084953815650726c30e053a looped-back |
| 17:59.06 | lennert | i think i have all the pieces i need for my vt100 emulator now.. woot :) |
| 18:10.51 | ka6sox | excellent |
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| 20:17.44 | lennert | receiver + transmitter fit nicely in 34 slices |
| 21:06.21 | lennert | if i write "dest <= a xor ((b and c) or ((not b) and d));" i don't see why xst wouldn't use a LUT4 for the job.. |
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