| 02:02.33 | lennert | w00000t |
| 02:02.49 | lennert | i made the xilinx synthesizer segfault |
| 02:02.55 | lennert | ========================================================================= |
| 02:02.55 | lennert | * Low Level Synthesis * |
| 02:02.55 | lennert | ========================================================================= |
| 02:02.55 | lennert | make: *** [destest.ngc] Segmentation fault |
| 02:02.59 | lennert | i rock :P |
| 02:03.01 | ka6sox-office | ha ha ha |
| 02:03.50 | lennert | it's kind of easy, too |
| 02:04.01 | lennert | just write blah <= "1111"; outside a process |
| 02:04.10 | lennert | and then inside a process, write blah <= "0000"; |
| 02:05.21 | ka6sox-office | bad bad form :) |
| 02:05.46 | ka6sox-office | looks like a Bozo No No to me. |
| 02:05.50 | lennert | ka6sox-office: i deleted the assignment outside the process but didn't :wq before i resynthesized |
| 02:06.48 | ka6sox-office | ah...that would do it. |
| 02:06.58 | ka6sox-office | must eat now...back later |
| 04:01.12 | *** join/#openjtag dot (n=ka6sox@adsl-66-159-198-116.dslextreme.com) |
| 04:12.07 | key2 | someone knows a device that could read fast a flash linked to a proc (MIPS) that has a JTAG/EJTAG interface ? |
| 04:13.20 | ka6sox | key2, a couple of people are working on one the has USB interface :) |
| 04:13.35 | ka6sox | but its not quite done :) |
| 04:13.44 | ka6sox | very soon |
| 04:13.46 | key2 | like who ? |
| 04:13.52 | ka6sox | ep1220 |
| 04:14.11 | key2 | ka6sox: that's his nick ? |
| 04:14.30 | ka6sox | ep1220 |
| 04:15.10 | ka6sox | I just received boards today and will be building them tommorrow. |
| 04:15.18 | ka6sox | and then starting testing. |
| 04:16.41 | ka6sox | you need MIPS and ejtag? |
| 04:17.45 | key2 | yeah |
| 04:17.56 | key2 | I made also a USB cable for ejtag |
| 04:18.05 | key2 | based on the ftdi2232 |
| 04:18.13 | key2 | and a scenix microcontroller |
| 04:18.20 | ka6sox | that is what this board is too..but no controller. |
| 04:18.28 | key2 | well that's slow then |
| 04:18.32 | ka6sox | just the 2232. |
| 04:18.42 | ka6sox | how fast are you looking for? |
| 04:18.46 | key2 | 2232 can perform read/write/readwrite |
| 04:18.55 | key2 | but not EJTAG_DMA_ control |
| 04:18.59 | ka6sox | over 6mbits? |
| 04:19.04 | key2 | no |
| 04:19.06 | ka6sox | okay I see what you mean |
| 04:19.14 | key2 | 1mb would be great |
| 04:19.23 | key2 | but his cable just uses the ftdi lib |
| 04:19.37 | key2 | so it's limited to the JTAG function and doesn't really now about ejtag |
| 04:19.55 | ka6sox | that is where I think that we are going to have to rewrite the libftdi driver. |
| 04:20.13 | ka6sox | (for better jtag control) |
| 04:20.30 | key2 | so it's basically slow since everytime he has to send on ReadWrite get the answer and send an other one so it's not worth using USB for that |
| 04:20.56 | key2 | it's not really possible and even if it was, it would't help |
| 04:21.10 | key2 | since in ejtag, you have to wait untill some flags are set |
| 04:21.16 | key2 | so basically u have to read non stop |
| 04:21.23 | ka6sox | k |
| 04:21.24 | key2 | untill you get the value you were looking for |
| 04:21.37 | ka6sox | so you have to do a comparison then? |
| 04:21.41 | key2 | but everytime you do a READ, you send a usb frame of 4096 byte and only 32 of them are usefull |
| 04:21.53 | key2 | yeah |
| 04:22.03 | key2 | that's why I was using a Scenix microcontroller |
| 04:22.31 | key2 | http://www.parallax.com/detail.asp?product_id=SX48BD |
| 04:22.37 | ka6sox | I was interested in using a Pic micro. |
| 04:22.45 | key2 | pic are too slow |
| 04:22.59 | key2 | look at the price of those one |
| 04:23.38 | ka6sox | 20 MIPS is too slow? |
| 04:23.54 | key2 | yeah |
| 04:24.00 | key2 | 75Mips is already too slow |
| 04:25.08 | key2 | 6mb/s = 750kB/s |
| 04:25.56 | key2 | and it takes you much more than 100 8bit instructions to do a ejtag_dma_read |
| 04:27.34 | ka6sox | hmmm... |
| 04:28.08 | ka6sox | I thought that ejtag allowed you to set the flags and then just read what you wanted. |
| 04:28.32 | ka6sox | instead of having to read the stream and wait until what you wanted to come back. |
| 04:28.50 | ka6sox | brb...putting child to bed. |
| 04:31.23 | key2 | no |
| 04:31.33 | key2 | everytime you wanna do a ejta_dma_read |
| 04:32.49 | key2 | you have to do few ReadWrite() |
| 04:33.00 | key2 | then get the EJTAG registers back |
| 04:33.13 | key2 | it takes a while |
| 04:33.15 | key2 | believe |
| 04:33.18 | key2 | believe me |
| 04:42.29 | ka6sox | I do |
| 04:43.43 | ka6sox | sounds like what you need is an Abatron |
| 04:55.22 | key2 | I need a very very cheap 32bit microcontroller |
| 04:56.01 | ka6sox | ya...but bitbanging 6mb/sec isn't fun. |
| 04:57.07 | key2 | yeah |
| 04:57.08 | key2 | right now |
| 04:57.17 | key2 | it takes me 12s to read 64Kb of memory |
| 04:57.52 | key2 | which means 12min to read the whole memory |
| 04:57.56 | key2 | tooo slow |
| 04:58.12 | ka6sox | takes us 40 minutes to write 256kB of bootloader with the IXP420 |
| 04:58.40 | ka6sox | (with a wiggler) this tool should get it down to about 6 minutes. |
| 04:59.20 | key2 | wigller ? |
| 04:59.30 | key2 | what tool shout do it in 6min ? |
| 05:00.33 | key2 | i'm scared ending up to do it with a fpga |
| 05:00.54 | ka6sox | thats what I'm playing with...a Spartan3 board. |
| 05:01.04 | ka6sox | it can easily do 6mb/sec |
| 05:01.07 | ka6sox | and do the comp too. |
| 05:01.10 | key2 | vhdl or verilog ? |
| 05:01.12 | ka6sox | vhdl |
| 05:01.17 | ka6sox | (xilinx) |
| 05:01.18 | key2 | fuck |
| 05:01.21 | key2 | prefer verilog |
| 05:01.23 | key2 | yeah |
| 05:01.26 | key2 | I have one of those board |
| 05:01.33 | key2 | Digilent one |
| 05:01.39 | key2 | with spartan3 |
| 05:01.40 | ka6sox | thats the one. |
| 05:01.45 | ka6sox | and 1MB of memory |
| 05:01.46 | key2 | 100 bucks |
| 05:01.59 | key2 | what do you do in life ? |
| 05:02.21 | ka6sox | Broadcast engineer/Hardware developer |
| 05:02.31 | ka6sox | (and play with VHDL stuffs) |
| 05:02.50 | key2 | ok |
| 05:02.56 | key2 | normally if I take a small fpga |
| 05:02.57 | ka6sox | you? |
| 05:03.07 | key2 | let's say xc2s familly |
| 05:03.17 | key2 | can I make it ? |
| 05:04.21 | ka6sox | what TZ are you in? |
| 05:04.27 | key2 | TZ ? |
| 05:04.36 | ka6sox | Timezone. |
| 05:04.41 | key2 | oh |
| 05:04.43 | key2 | paris/fr |
| 05:04.46 | key2 | it's 6 am |
| 05:04.49 | ka6sox | morning. |
| 05:04.54 | key2 | AM |
| 05:04.55 | key2 | :) |
| 05:04.56 | key2 | yeah |
| 05:04.57 | ka6sox | its 9pm here. |
| 05:05.02 | key2 | need to sleep |
| 05:05.04 | ka6sox | UTC-8 |
| 05:05.07 | key2 | u're in california ? |
| 05:05.10 | ka6sox | ya |
| 05:05.14 | key2 | wherea bout |
| 05:05.19 | ka6sox | Santa Barbara |
| 05:05.23 | key2 | oh :) |
| 05:05.28 | key2 | i used to live in LA |
| 05:05.29 | ka6sox | expensive. |
| 05:05.38 | ka6sox | where? I grew up in OC. |
| 05:05.54 | key2 | west hollywood |
| 05:06.11 | ka6sox | ah...what took you to paree? |
| 05:06.24 | key2 | paree ? |
| 05:06.39 | ka6sox | paris |
| 05:06.46 | key2 | i'm french |
| 05:06.52 | key2 | the question should be what took me to la :) |
| 05:06.53 | ka6sox | good reason. |
| 05:07.02 | ka6sox | okay what took you here? |
| 05:07.08 | key2 | a chickj |
| 05:07.10 | key2 | -j |
| 05:07.28 | key2 | a girl I met here few years ago |
| 05:07.42 | ka6sox | ah...did you bring her back? |
| 05:07.52 | key2 | fuck no :) |
| 05:08.07 | ka6sox | ah... |
| 05:08.18 | ka6sox | I'm here most of the time... |
| 05:08.23 | key2 | I had no money there so I was workin in bars, and then I used to fuck around so much with other girls that my relation with her had no sence |
| 05:08.39 | key2 | so after I realized that I'm wasting my time there, I came back |
| 05:08.55 | ka6sox | what are you doing now? |
| 05:09.09 | key2 | engineering.. |
| 05:09.12 | key2 | in a DSL company |
| 05:09.21 | ka6sox | fun. |
| 05:09.24 | key2 | yeah |
| 05:09.36 | ka6sox | there is a good group here... |
| 05:09.38 | key2 | that's what I originally studdied, not bartending :) |
| 05:10.03 | key2 | so basically |
| 05:10.12 | key2 | I need to make a cable that would be very chip and very fast |
| 05:10.36 | ka6sox | sounds like a S3 or Virtex2 type would do it. |
| 05:10.37 | key2 | so since a pic and a scenix won't make it (not fast enough) |
| 05:10.52 | key2 | well S3 are first BGA (for most of them) |
| 05:11.03 | key2 | then I don't need that amount of gate for just driving a jtag |
| 05:11.09 | key2 | so I'm planning on something smaller |
| 05:11.11 | key2 | and cheaper |
| 05:11.14 | ka6sox | CPLD? |
| 05:11.21 | key2 | no |
| 05:11.23 | key2 | small fpga |
| 05:11.27 | key2 | like I said |
| 05:11.43 | ka6sox | what are you going to feed it with? |
| 05:11.51 | key2 | cx2s15 or xc2s30 should make it |
| 05:12.28 | key2 | well from one side, I have to take the data, and the type of instruction |
| 05:12.37 | key2 | and from the other, I have to read/write on the jtag |
| 05:12.39 | ka6sox | sounds like you dont' need a lot of pins. |
| 05:12.50 | key2 | not at all |
| 05:13.20 | ka6sox | I like the Coolrunner II's that I"m now playing with. |
| 05:13.23 | key2 | but don't know if I should use a uC with it or if it would be a waste |
| 05:13.36 | key2 | how many logical gate? |
| 05:13.47 | ka6sox | something like 15K |
| 05:14.33 | key2 | I think it's fine |
| 05:14.47 | key2 | but don't really know how to implement it |
| 05:16.26 | ka6sox | 323MHz parts. |
| 05:20.46 | ka6sox | gotta run now...be back on later...I'm here a lot..unless I"m not :) |
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| 06:48.36 | ka6sox | morning ep1220 boards arrived. |
| 06:54.41 | ep1220 | ka6sox: hello, hope all went well with Your son's surgery |
| 06:54.56 | ka6sox | ep1220, yes..hes finally feeling better. |
| 06:55.04 | ka6sox | almost a week later :) |
| 06:55.28 | ep1220 | good to hear. |
| 06:55.32 | ka6sox | yes. |
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| 09:20.39 | lennert | ka6sox: you have any vhdl to share yet? |
| 09:21.59 | ka6sox | I should have it up by weeks end. |
| 09:22.15 | ka6sox | right now I've got to get a presentation going. |
| 09:34.37 | lennert | okay |
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| 12:01.39 | key2 | ep1220? there? |
| 12:01.55 | ep1220 | hello |
| 12:04.24 | key2 | I heard you made a jtag cable with the ft2232 |
| 12:04.26 | key2 | ? |
| 12:04.38 | ep1220 | yes. |
| 12:04.52 | key2 | is it fast for ejtag ? |
| 12:05.16 | ep1220 | good question :-) |
| 12:05.22 | key2 | Because I tryed |
| 12:05.30 | key2 | and it's even slower than a // cable |
| 12:06.09 | ep1220 | Did You use for debugging or Flashing ? |
| 12:06.10 | key2 | since there are someflags and everytime you send a ReadWrite, you have to wait for the answer |
| 12:06.15 | key2 | Flashing |
| 12:06.41 | ep1220 | latency is a problem for this cable |
| 12:06.59 | key2 | I ended up putting my code in a Scenix 75Mips microcontroller |
| 12:07.13 | key2 | and right now, for reading 64Kb, it takes me about 16s |
| 12:07.20 | key2 | which is the same as the // port |
| 12:08.05 | ep1220 | what is the JTAG clock rate you get with then Scenix ? |
| 12:08.47 | ep1220 | s/then/the |
| 12:09.26 | key2 | well the Scenix is a 75Mips proc |
| 12:09.42 | key2 | If I don't put delay between the TCK, the broadcom doesn't even answer |
| 12:09.52 | key2 | so I'm faster than the broadcom for that |
| 12:10.10 | ep1220 | ok |
| 12:10.22 | key2 | but the probleme is that the Scenix is a 8bit proc and I have to convert the instructions to 32Bit so it takes almost 4x more time |
| 12:11.24 | ep1220 | can't You use the "delay" time to do some processing, so You hide the 32/8 conversion. |
| 12:15.20 | ep1220 | i am not familiar with this uP: how does it connect to the PC ? USB ? |
| 12:18.46 | key2 | usb |
| 12:18.58 | key2 | it's like a Pic Microchip |
| 12:19.00 | key2 | same arch |
| 12:20.28 | key2 | brb |
| 12:20.40 | ep1220 | k |
| 12:21.02 | ep1220 | You do 64Kbyte in 16 seconds .i.e 4000bytes per second |
| 12:21.19 | key2 | yeah |
| 12:21.23 | ep1220 | = 1 32bit word per USB transfer -> maybe USB is limiting You here |
| 12:22.25 | ep1220 | Do you handshake each 32bit word with the host PC ? |
| 12:22.38 | key2 | no |
| 12:22.41 | key2 | I get a frame |
| 12:22.46 | key2 | but I found why it was so slow |
| 12:22.57 | ep1220 | i am curious |
| 12:23.09 | key2 | let's say I could bring it to 7s for 64kb |
| 12:23.14 | key2 | would it be interesting ? |
| 12:24.33 | key2 | hold on, I need to reboot |
| 12:24.47 | key2 | unless you have a solution for when HyperTerminal is dead and you can't kill it |
| 12:25.07 | key2 | brb |
| 12:25.12 | ep1220 | sorry, never been there |
| 12:29.26 | [g2] | morning ep1220 |
| 12:29.39 | ep1220 | morning [g2] |
| 12:29.48 | [g2] | how's the board ? |
| 12:30.13 | ep1220 | sofar i am quite happy with it :-) |
| 12:30.28 | [g2] | great! |
| 12:30.42 | ep1220 | i can do same things as with my earlier prototype. |
| 12:30.51 | [g2] | excellent |
| 12:31.01 | [g2] | when do they go up for sale ? |
| 12:31.13 | ep1220 | Over the weekend i plan to build 3 more. |
| 12:31.47 | ep1220 | if these work as well then i think i can sell some. |
| 12:32.04 | [g2] | super |
| 12:32.24 | [g2] | what will they cost ? |
| 12:32.54 | ep1220 | i must check my invoices. |
| 12:33.13 | [g2] | you can send me an e-mail later after you check |
| 12:34.14 | ep1220 | It also depends a bit on over how many boards I split the setup-cost. |
| 12:34.35 | ep1220 | the partscost is in the order of 50$ |
| 12:34.50 | ep1220 | (excluding PCB) |
| 12:35.27 | [g2] | hey I know you're not doing this to get rich immediately :) |
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| 12:35.35 | key2 | back |
| 12:35.46 | key2 | ep1220: ok it takes me now about 8s to read 64k |
| 12:36.22 | ep1220 | key2: a good improvement |
| 12:36.37 | key2 | yeah |
| 12:36.39 | key2 | but still too much |
| 12:36.56 | key2 | I don;t wanna end up doing that with an FPGA since it's gonna cost more |
| 12:37.11 | key2 | right now just with the ft2232 and sc, my cable costs about $15 |
| 12:37.13 | key2 | which is ok |
| 12:37.23 | [g2] | last I checked a Scenix dev kit was _very_ expensive :) |
| 12:37.53 | ep1220 | the ft2232C alone is around 15$ in small quantities |
| 12:38.05 | key2 | [g2] http://www.parallax.com/detail.asp?product_id=SX28AC/SS |
| 12:38.12 | key2 | ep1220: NO |
| 12:38.16 | key2 | it's about $5 |
| 12:38.53 | key2 | http://www.parallax.com/detail.asp?product_id=604-00033 |
| 12:38.53 | key2 | ok $8 |
| 12:38.53 | key2 | which is half of what you're announcing |
| 12:39.04 | [g2] | key2 have they released the dev kit's for the Scenix parts ? |
| 12:39.15 | key2 | I already made one myself |
| 12:39.23 | key2 | so I don't care about their dev kit |
| 12:39.29 | key2 | the problem is not that |
| 12:39.47 | key2 | the problem is that for reading EJTAG, it still takes too long even at 75Mips since it's a 8bit proc |
| 12:40.30 | key2 | so I don't know if it's better to have a cable that can read 4Mb in about 10mins for $15 or 4Mb in about 40s for about $50 |
| 12:40.38 | [g2] | key2 so you built your own compiler/toolchains for the ubicom chip ? |
| 12:40.39 | key2 | I need some opinion on htat |
| 12:40.58 | key2 | g2: no, that's a Microchip PIC core |
| 12:41.11 | key2 | so you can use the free one |
| 12:41.12 | key2 | .. |
| 12:41.50 | [g2] | key2 so there was enough info in the DS to download to the chip and debug too ? |
| 12:41.53 | key2 | [g2] otherwise C2C is free |
| 12:41.55 | key2 | .. |
| 12:42.20 | ep1220 | key2: You are right, last time i looked at the FTDI site i tought it was 8GBP |
| 12:42.52 | [g2] | time does fly when one is having fun :) |
| 12:43.13 | key2 | but the question is what sould I make, a cable that costs $15 and that reads 4MB in about 10 15 mins or an otherone that costs $50 and reads 4Mb in about 40s |
| 12:44.33 | [g2] | key2 you do EJTAG ? |
| 12:44.40 | key2 | yeah |
| 12:44.48 | key2 | on JTAG i could read it way faster |
| 12:44.55 | key2 | that's for EJTAG (broadcom mips) |
| 12:45.06 | [g2] | yeah. I know |
| 12:45.26 | key2 | [g2] so $15 one or $50 one |
| 12:45.29 | [g2] | there's a large number of wrt54g hackers |
| 12:46.10 | [g2] | I've got a couple lying around |
| 12:47.17 | ep1220 | key2: if the 15$ one is faster too, this is not hard to answer |
| 12:47.54 | [g2] | key2 are you focusing on EJTAG or JTAG ? |
| 12:55.10 | ep1220 | key2: sorry, i misread Your numbers,: i read 4Mb in 10 seconds not 10 minutes ... |
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| 13:28.09 | key2 | yeah |
| 13:28.10 | key2 | so ? |
| 13:28.14 | key2 | what's the most interesting |
| 13:28.40 | key2 | $15 and takes 15mins to read or $50 and it takes 40s |
| 13:29.12 | ep1220 | for me the faster one would be worth the extra $ |
| 13:30.18 | ep1220 | however if just wanted to unbrick a dead device i would buy the 15$ cable |
| 13:33.16 | ep1220 | BTW: Are these prices for completely assembled devices ? |
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| 22:37.46 | key2 | anyone has some experiances with Verilog ? |
| 22:39.26 | ka6sox-office | Verilog? whats that? *he he* |
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| 22:40.13 | lennert | ka6sox-office: it's vhdl for people who hate ada :) |
| 22:40.27 | key2 | verilog looks more like C |
| 22:40.32 | key2 | and vhdl looks more like ada |
| 22:40.50 | lennert | key2: yup |
| 22:40.57 | ka6sox-office | no wonder I like VHDL better. |
| 22:41.05 | key2 | How comes |
| 22:41.11 | lennert | ka6sox-office doesn't like C |
| 22:41.13 | key2 | if you're more familiar with c |
| 22:41.21 | lennert | i like C more than ada, but i still prefer vhdl |
| 22:41.27 | key2 | why |
| 22:41.59 | lennert | key2: probably simply because i'm used to it |
| 22:42.07 | key2 | ok |
| 22:42.11 | key2 | maybe you could answer me |
| 22:42.23 | key2 | if I have a port that is an Input output |
| 22:42.39 | key2 | do I have to say that i wanna turn it into input mode or output mode ? |
| 22:43.00 | key2 | or is it just considered as a wire and I have to manage to put the right thing behind to manage it |
| 22:43.38 | lennert | key2: in vhdl, an inout port is a port that is an output, put you can still read the value that you wrote into it yourself |
| 22:43.52 | lennert | key2: if you want to have a pin that can be both an input and an output, you want a tristate buffer |
| 22:43.59 | lennert | key2: i dunno if verilog has builtin support for those... :-/ |
| 22:44.59 | key2 | so basically, you put a tristate FF and with a ChipEnable pin |
| 22:45.07 | key2 | and if you wanna write, u enable it |
| 22:45.17 | key2 | otherwise you disable it so it's like the pin is in the air |
| 22:45.18 | key2 | ? |
| 22:51.07 | lennert | key2: if that's possible, yeah |
| 22:51.14 | lennert | key2: maybe look in the docs that came with your synthesis tool |
| 22:51.20 | lennert | key2: that should tell you what you can use |
| 22:51.30 | lennert | key2: if you use the xilinx webpack, check out xst.pdf |
| 23:01.24 | key2 | The inout port in Verilog is analogous to a bi-directional I/O pin on |
| 23:01.24 | key2 | the device with the data flow for output versus input being |
| 23:01.24 | key2 | controlled by the enable signal to the tristate buffer. |
| 23:01.52 | lennert | okay |
| 23:01.55 | lennert | sounds what you need then |
| 23:02.01 | key2 | yeah |
| 23:02.10 | key2 | so it's build in |
| 23:02.17 | lennert | good to know |
| 23:03.36 | key2 | but I dunno where is the wire saying it's OutEnable |
| 23:03.46 | key2 | module EXAMPLE (A, B, C, D, E); |
| 23:03.46 | key2 | input A, B, C; |
| 23:03.46 | key2 | output D; |
| 23:03.46 | key2 | inout E; |
| 23:03.46 | key2 | wire D, E; |
| 23:03.47 | key2 | ... |
| 23:03.49 | key2 | assign E = oe ? A : 1’bz; |
| 23:03.51 | key2 | assign D = B & E; |
| 23:03.53 | key2 | ... |
| 23:03.55 | key2 | endmodule |
| 23:04.05 | key2 | in this example, where the hell did they declare oe |
| 23:05.12 | lennert | dunno.. |
| 23:06.14 | key2 | i got an otherone that seams to be clearer |
| 23:06.18 | key2 | module test (a, oe, o); |
| 23:06.18 | key2 | inout [2:0] a ; |
| 23:06.18 | key2 | input [3:0] oe ; |
| 23:06.18 | key2 | inout o ; |
| 23:06.18 | key2 | wire bus; |
| 23:06.19 | key2 | assign bus = oe[2] ? a[2] : 'bz; |
| 23:06.21 | key2 | assign bus = oe[1] ? a[1] : 'bz; |
| 23:06.23 | key2 | assign bus = oe[0] ? a[0] : 'bz; |
| 23:06.25 | key2 | PULLUP i0 (.O(bus)); |
| 23:06.27 | key2 | PULLUP i1 (.O(a[0])); |
| 23:06.29 | key2 | assign o = oe[3] ? bus : 'bz; |
| 23:06.31 | key2 | endmodule |
| 23:29.05 | *** join/#openjtag ByronT (i=ByronT@nslu2-linux/ByronT) |