| 00:48.33 | lennert | ka6sox-office: ping? |
| 00:49.34 | ka6sox-office | pong |
| 00:49.37 | lennert | whee |
| 00:49.46 | lennert | i have to interface two different clock domains |
| 00:49.49 | ka6sox-office | wazzup |
| 00:50.01 | lennert | and i thought you might be able to lend me a hand |
| 00:50.13 | ka6sox-office | could be! |
| 00:50.50 | lennert | i have a 50mhz clock for some logic, and 1.8432mhz for an uart |
| 00:50.53 | lennert | the uart works fine |
| 00:51.14 | lennert | the clocks aren't derived from each other |
| 00:51.22 | ka6sox-office | yep |
| 00:51.33 | lennert | so, what i thought was.. |
| 00:51.57 | lennert | have two t flipflops |
| 00:52.05 | lennert | one of them driven by clock 1, other one by clock 2 |
| 00:52.08 | lennert | xor their Q outputs |
| 00:52.32 | lennert | if that is 1, the 1-deep 8-bit fifo is in the 'full' state, otherwise it's 'empty' |
| 00:52.44 | lennert | does that make sense? |
| 00:52.50 | lennert | (i'm trying to solve this generically) |
| 00:53.34 | ka6sox-office | you want to syncronize the 50mhz to 1.8432? |
| 00:53.48 | lennert | i want the 50mhz logic to be able to send stuff over serial, and receive stuff |
| 00:53.54 | lennert | so two ways |
| 00:55.03 | ka6sox-office | give me 2 minutes here. |
| 00:55.06 | lennert | np! |
| 00:55.15 | lennert | today is my no sleep day |
| 00:55.17 | lennert | :) |
| 00:55.28 | ka6sox-office | ugh |
| 01:03.32 | ka6sox-office | if you use overflow then it makes sense. |
| 01:03.38 | ka6sox-office | (or a carry bit) |
| 01:03.38 | lennert | 'overflow' |
| 01:03.40 | lennert | ? |
| 01:04.01 | ka6sox-office | 8bit counter with "overflow" or carry bit (so that you can chain them) |
| 01:04.39 | lennert | well |
| 01:04.41 | ka6sox-office | when I get home on my dev system I can look at the incantation. |
| 01:04.43 | lennert | actually, i have two t-flipflops |
| 01:04.52 | ka6sox-office | that will do. |
| 01:04.53 | lennert | XORed they are the 'fifo status' indication (empty/full) |
| 01:04.56 | lennert | and a separate 8 bit register |
| 01:05.06 | lennert | that 8 bit register is a 'holding area' for TX/RX bytes |
| 01:05.07 | ka6sox-office | just treat them as fifo's |
| 01:05.12 | lennert | well |
| 01:05.15 | lennert | my fifo is 1 deep |
| 01:06.04 | ka6sox-office | same with mine...I should send you some code I did for handling a 50mhz bus talking to a ~712khz bus |
| 01:06.14 | lennert | okay |
| 01:06.22 | lennert | since it's not a totally crazy idea, i'll try to implement it |
| 01:06.22 | ka6sox-office | and the busses were different sizes too. |
| 01:06.29 | ka6sox-office | not crazy |
| 01:06.33 | lennert | the two t flipflops was the easiest i could come up with |
| 01:06.36 | lennert | different clock domains suck |
| 01:06.46 | ka6sox-office | treat them separatly |
| 01:06.49 | lennert | yeah |
| 01:06.50 | ka6sox-office | and flag them |
| 01:06.57 | lennert | if you want deeper fifos i guess you have to use gray coding or something |
| 01:07.18 | ka6sox-office | so you would signal the TX buffer (to the uart) and say that you have a byte to send |
| 01:07.30 | ka6sox-office | when its done is sends back the "done' flag |
| 01:07.35 | lennert | yes, that's the idea |
| 01:07.43 | lennert | the sender and receiver have an 'enable' |
| 01:07.49 | ka6sox-office | and likewise for the RX |
| 01:07.55 | lennert | 50mhz clock up while enable active -> byte gets loaded into fifo |
| 01:08.06 | ka6sox-office | you have to have "flow control" with that big of a clock difference" |
| 01:08.11 | lennert | 1.8432mhz clock up while enable active and fifo is full -> byte gets unloaded |
| 01:08.22 | lennert | the XOR of the two t flipflops is the 'fifo full' signal |
| 01:08.24 | ka6sox-office | exactly |
| 01:08.29 | ka6sox-office | works for me! |
| 01:08.34 | lennert | the TX keeps enable high until the load is successful |
| 01:08.36 | lennert | okay! |
| 01:10.39 | ka6sox-office | you send me your code too!! |
| 01:10.45 | lennert | :) |
| 01:10.45 | ka6sox-office | and i'll look too! |
| 01:10.52 | lennert | i have a subversion tree that has all my crap in it |
| 01:11.04 | lennert | not in a public place yet, i couldn't get svnweb to work |
| 01:11.15 | lennert | (any recommendations for something like svnweb?) |
| 01:11.28 | ka6sox-office | svk is what I'm looking at for s3projects. |
| 01:12.25 | lennert | sovuk |
| 01:13.23 | lennert | i'll have a look |
| 01:13.27 | lennert | SVN::Web was dependency hell |
| 01:13.38 | lennert | ka6sox-office: i have supervga pong now |
| 01:13.45 | ka6sox-office | sweet! |
| 01:13.53 | lennert | ka6sox-office: finally got the clock manager thingy in the spartan to work |
| 01:14.50 | lennert | the best pixel clock rate for 640x480 turned out to be 50.000MHz times 17/24 :) |
| 01:15.08 | lennert | i.e. 35.416MHz-ish |
| 01:16.04 | ka6sox-office | fast. |
| 01:27.25 | lennert | ka6sox-office: for 1024x768 in 80Hz it's about 77MHz |
| 01:28.28 | lennert | ka6sox-office: my vt100 emulator calculates pixels 8 at a time so it doesn't really matter |
| 01:28.37 | lennert | ka6sox-office: (vt100 emulator's display part is done) |
| 01:36.20 | ka6sox-office | currently fixing Vservers...so I'll be a bit :) |
| 01:36.51 | [g2] | lennert are you using the block ram at all ? |
| 01:37.05 | lennert | [g2]: for the display buffer, yes |
| 01:37.16 | lennert | [g2]: and for font storage |
| 01:37.32 | [g2] | and the UART FIFO ? :) |
| 01:37.40 | lennert | uart fifo is just a bunch of flipflops |
| 01:37.44 | lennert | no block ram |
| 01:38.03 | [g2] | I'm suggesting a small 8 / 16 byte fifo |
| 01:38.26 | [g2] | ring buffer with a 3 bit or 4 bit register |
| 01:38.29 | lennert | that can in theory be added fairly easily, yes |
| 01:38.46 | lennert | it's mostly useful if you want to interface it with a cpu core |
| 01:38.56 | lennert | (which is what i'll be doing on the virtex board :) |
| 01:39.36 | [g2] | I'd think you'd want a wider interface for the virtex cpu |
| 01:39.51 | lennert | it's a win to be 16450-compatible |
| 01:40.07 | [g2] | 16550 ? |
| 01:40.19 | lennert | or that |
| 01:40.23 | lennert | anything 8250-derivative |
| 01:40.41 | [g2] | well the 450s and 550 have 14 byte fifo iirc |
| 01:40.53 | [g2] | and thresholding on the int generation |
| 01:41.00 | lennert | could be, yes |
| 01:41.20 | lennert | response times for a cpu core are more variable |
| 01:41.35 | lennert | for what i'm using it for right now, response time is not an issue and thus a single byte fifo suffices |
| 01:42.13 | [g2] | oh you're kicking ass, I'm just wondering where you are headed :) |
| 01:42.30 | [g2] | and wondering what the real underlying issues are |
| 01:43.04 | lennert | [g2]: other people are doing good work on the jtag front but i'll be trying that anyway, just for fun :) |
| 01:43.34 | [g2] | well there's no shortage of good work to be done in my mind |
| 01:43.40 | [g2] | the more the merrier |
| 01:43.49 | lennert | always enough asses to kick, you mean? |
| 01:43.51 | [g2] | doing good work that is |
| 01:44.33 | lennert | everyone here is kicking major ass |
| 01:45.40 | [g2] | IMHO we're in the final stretch of the open boxen |
| 01:46.27 | [g2] | this JTAG piece is the last key and the JTAG debugging is the icing on the cake |
| 01:48.00 | lennert | [g2], but the ixp4xx gate mask is not open sourced :) |
| 01:48.20 | [g2] | heh |
| 01:48.41 | lennert | some really has to do the open-source LEG |
| 01:48.44 | lennert | s/some/someone/ |
| 01:48.45 | [g2] | there's a guy around here that does X-rays for $25-30 |
| 01:49.01 | lennert | xrays of chips? |
| 01:49.13 | [g2] | it's an x-ray machine |
| 01:49.32 | lennert | not sure how useful that is for chips |
| 01:49.33 | [g2] | dunno the rs |
| 01:49.38 | [g2] | dunno the res |
| 01:49.59 | lennert | in any case, we don't need to look at intel's stuff, we'll just design something better :) |
| 01:50.20 | [g2] | did you see the PPC announcement ? |
| 01:50.33 | lennert | nope/ |
| 01:51.19 | [g2] | http://www.linuxdevices.com/news/NS7626583293.html |
| 01:51.35 | [g2] | won't be till late next year |
| 01:51.45 | [g2] | but they've got a good idea |
| 01:52.35 | lennert | 24 serdes! |
| 01:53.17 | [g2] | lennert wets pants |
| 01:53.39 | lennert | i want an fpga with 24 gige ethernet ports |
| 01:53.51 | lennert | (at an affordable price) |
| 01:54.50 | [g2] | I'd think a PC with 2 10G PCI-E cards would be close enough |
| 01:55.05 | lennert | not as fun |
| 01:55.11 | lennert | nor as powerful |
| 01:55.28 | [g2] | but _way_ cheaper |
| 01:55.39 | [g2] | that's the affordable part |
| 01:55.47 | lennert | sure, but it's not as if i have a real need to do 25 gigabit routing |
| 01:55.55 | lennert | (at the lowest possible cost) |
| 01:56.00 | lennert | just want more toys to play with |
| 01:56.04 | lennert | toys toys toys |
| 01:57.51 | lennert | okay, time to go to work |
| 02:05.35 | [g2] | :) |
| 02:05.51 | [g2] | so do you pull an all-night once a week ? |
| 02:13.38 | *** join/#openjtag dyoung-web (n=80ab9a96@nslu2-linux/dyoung) |
| 02:37.15 | lennert | [g2]: kind of, yeah |
| 02:37.22 | lennert | dyoung-web: whom are you trying to repell? |
| 02:37.30 | lennert | [g2]: sometimes twice :) |
| 02:38.06 | lennert | [g2]: today i have to pick up wife from the airport at 9am, which is a time that i haven't been awake at for a long long time now |
| 02:38.27 | lennert | [g2]: and i forgot to do some stuff at work, so i decided to go back to work (at 4am :) and just stay up |
| 02:41.05 | [g2] | lennert well godspeed and safe driving |
| 02:41.21 | dyoung-web | okay, that one was my fault. |
| 02:41.29 | dyoung-web | "wheres my prompt" |
| 02:41.39 | dyoung-web | because I forgot to install their shell. :/ |
| 02:42.06 | [g2] | heh |
| 02:42.20 | lennert | [g2]: you can't kill much when you're by bicycle |
| 02:42.37 | lennert | [g2]: i don't even have a car.. |
| 02:42.46 | dyoung-web | wear lots of blinky lights? |
| 02:43.04 | [g2] | are there two seats on the bike ? |
| 02:44.31 | lennert | [g2]: one seat :) |
| 02:44.56 | lennert | [g2]: well, we're used to that here.. anyway, it never gets really cold here, we just have the North Sea wind to deal with |
| 02:47.48 | [g2] | ahh... newlyweds :) |
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| 02:51.16 | ka6sox-away | okay lennert: I'm home. |
| 02:51.32 | ka6sox-away | where should I look for your files? |
| 02:57.51 | lennert | ka6sox-away: i don't actually have them in a publicly accessible place yet |
| 02:58.03 | lennert | ka6sox-away: i can send you a tarball of my current svn tree |
| 02:59.09 | lennert | ka6sox-away: after i finish mutilating this 'ere windows 2000 server, that is |
| 03:02.17 | ka6sox-away | lennert cool! |
| 03:02.21 | ka6sox-away | I'll add it :) |
| 03:06.04 | ka6sox-away | has anyone spoken to dyoung-web? |
| 03:08.19 | lennert | okay, let me get to that |
| 03:10.38 | lennert | oh this is so damn VILE |
| 03:11.02 | lennert | what i'm doing to this windows box is beyond words.. i love it |
| 03:16.13 | ka6sox-away | ow ow ow owwwww |
| 04:29.44 | lennert | ka6sox-away: http://www.wantstofly.org/~buytenh/vhdl/fifo.vhd |
| 04:29.56 | lennert | ka6sox-away: i didn't try synthesizing it yet, but does it look approx. okay? |
| 04:32.04 | lennert | hang on, reorganising |
| 04:32.47 | ka6sox-away | I never worried about the states...just used flags.... |
| 04:33.05 | lennert | they are flags here.. |
| 04:33.17 | ka6sox-away | when I wrote to the fifo I just told the next process to start and when it was finished just signal |
| 04:33.19 | lennert | but a_state='0' b_state='0' and a_state='1' b_state='1' both mean empty |
| 04:33.25 | ka6sox-away | I agree. |
| 04:33.45 | ka6sox-away | but its much simpler logic to just signal when thru. |
| 04:34.04 | lennert | can you reload? |
| 04:34.10 | ka6sox-away | yep |
| 04:35.02 | ka6sox-away | there ya go...much easier to read. |
| 04:35.15 | ka6sox-away | try synthesizing this and see where it blows up :) |
| 04:35.21 | ka6sox-away | (doesnt' look like it will) |
| 04:35.56 | lennert | yeah, i'll test |
| 04:36.12 | lennert | i'll use slide switches as inputs and leds as outputs |
| 04:36.32 | ka6sox-away | ah....similar to what you were going to have dyoung do? |
| 04:36.33 | ka6sox-away | :) |
| 04:36.39 | lennert | sssssh :) |
| 04:36.45 | ka6sox-away | he he |
| 04:36.57 | dyoung-web | hahahahahaha |
| 04:37.32 | ka6sox-away | psssst...dyoung-web: use this as a starting place...(don't tell lennert) |
| 04:38.00 | lennert | (i don't care if dyoung copies someone else's vhdl, 'cause that way he'll also learn how it's done) |
| 04:38.29 | ka6sox-away | yes but I want proper semaphores :) |
| 04:41.00 | lennert | ka6sox-away: how do you mean? |
| 04:41.41 | ka6sox-away | j/k |
| 04:42.01 | ka6sox-away | when you reorged it became clear... :) |
| 04:42.08 | lennert | hehe |
| 04:42.24 | lennert | the solution wasn't clear to me until i implemented it |
| 04:46.26 | lennert | 'tis almost time for me to go |
| 04:47.29 | ka6sox-away | go...lets see...this is a no sleep night? |
| 04:47.32 | ka6sox-away | 7am? |
| 04:47.38 | lennert | yeah |
| 04:47.51 | lennert | have to pick up other half from the airport round 9 |
| 04:48.02 | ka6sox-away | oh yeah...wednesday! w00t |
| 04:48.22 | lennert | :) |
| 04:48.28 | lennert | double you zero zero tee |
| 04:52.05 | lennert | ka6sox-away: i think there's still a problem if wr_state toggles before rd_port does |
| 04:52.44 | lennert | ka6sox-away: i think wr_state should be delayed one write clock |
| 04:53.21 | ka6sox-away | it can become metastable if you are looking at rising_edge for both. |
| 04:53.30 | lennert | yes |
| 04:53.36 | lennert | that's the case i'm worried about |
| 04:54.08 | ka6sox-away | you can always look at falling edge too! |
| 04:54.12 | lennert | but well.. that'd reduce the performance of the fifo to half.. |
| 04:54.20 | lennert | ka6sox-away: falling edge where? |
| 04:54.41 | lennert | ka6sox-away: you want wr_state to activate on the falling edge? |
| 04:54.54 | lennert | ka6sox-away: what if there is a valid falling edge _before_ the rising edge? |
| 04:55.21 | lennert | rd_state xor wr_state can go to zero just after a rising wr_clock edge |
| 04:55.42 | lennert | in which case the falling edge would set wr_state, and the next rising edge would set rd_port |
| 04:55.46 | ka6sox-away | doesnt' matter you are only looking at level. |
| 04:56.08 | lennert | ? |
| 04:56.37 | lennert | woosh.. that's the sound of ka6sox-away going over my head |
| 04:56.43 | ka6sox-away | distracted here.... |
| 04:56.47 | lennert | np |
| 04:56.47 | ka6sox-away | 1 minute... |
| 05:05.45 | lennert | i'm thinking just to pipeline 'rd_state xor wr_state' in the reader |
| 05:05.54 | lennert | signal blah : std_logic; |
| 05:06.00 | lennert | blah <= rd_state xor wr_state; |
| 05:06.12 | lennert | if rising_edge(rd_clock) and rd_enable = '1' and blah = '1' |
| 05:06.13 | lennert | ... |
| 05:06.43 | lennert | hmmmm |
| 05:06.58 | lennert | i should also export "rd_state xor wr_state" as fifo_full :P |
| 05:07.08 | ka6sox-away | you could. |
| 05:08.40 | lennert | new version uploaded that exports fifo_full |
| 05:09.05 | lennert | whoops, should have been an inout |
| 05:09.07 | ka6sox-away | okay I need to take care of my wife. |
| 05:09.20 | ka6sox-away | signals dont care |
| 05:09.30 | lennert | okay |
| 05:09.37 | lennert | i'll run soon, so catch you later |
| 05:09.39 | lennert | thanks for your help |
| 05:10.51 | ka6sox-away | np |
| 05:11.40 | lennert | new version uploaded |
| 05:11.46 | lennert | this delays fifo_full by one read clock |
| 05:12.24 | lennert | will stare at it a bit more on the train |
| 05:28.39 | lennert | ka6sox-away: this version is kickass |
| 05:33.45 | ka6sox-away | cool! |
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| 06:25.49 | ka6sox-away | morning |
| 06:25.58 | ka6sox-away | ya..I am always here :) |
| 06:26.10 | ka6sox-away | except when I'm not. |
| 06:26.28 | ep1220 | maybe the PC is right beside Your bed :-) |
| 06:32.00 | vmaster | heh, mine is - but still there are hours when i simply sleep |
| 06:32.31 | ka6sox-away | me too...but its about my bed time here GMT-7 |
| 06:33.04 | ka6sox-away | this is my lappy and thats where it spends a lot of time. |
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