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| 13:04.11 | [g2] | prpplague hey CONGRATS! Hack-a-day ! |
| 13:05.12 | [g2] | http://www.hackaday.com/entry/1234000420064224/ |
| 13:18.48 | prpplague | [g2]: yea thanks, i appreciate it |
| 13:19.04 | prpplague | [g2]: :) |
| 13:50.31 | [g2] | prpplague that's cool, I know you've been hacking on that for awhile ! I'm glad to see someone recognized the value |
| 13:52.38 | lennert_ | whee, my uart works. kind of. |
| 13:56.38 | prpplague | [g2]: thanks, it was mainly done as a learning excercise |
| 13:56.46 | prpplague | [g2]: but it turnout pretty cool |
| 13:57.00 | prpplague | [g2]: my son was watching videos with it last night |
| 13:57.21 | prpplague | [g2]: hehe, now if i could get this s3c2410 board booting......... |
| 13:59.10 | lennert_ | prpplague: what board? |
| 14:12.56 | prpplague | lennert_: new custom board |
| 14:13.49 | lennert_ | ah |
| 14:13.58 | lennert_ | kyllikki and fluffy are the s3c2410 experts |
| 14:14.18 | lennert_ | not sure if fluffy is on freenode, but kyllikki should be |
| 14:15.40 | prpplague | lennert_: yea fluffy is on #mtd |
| 14:16.06 | prpplague | lennert_: kyllikki usualy hangs on #debian-arm |
| 14:16.14 | lennert_ | yeah |
| 14:17.27 | prpplague | hehe |
| 14:17.34 | prpplague | ./me has been on irc for a long time |
| 14:17.40 | prpplague | ek |
| 14:17.43 | prpplague | can't type |
| 14:18.11 | lennert_ | me.. since 1999 but i only started using it for tech stuff round 2003 |
| 14:18.16 | lennert_ | i met my wife on irc :) |
| 14:18.28 | prpplague | lennert_: hehe cute |
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| 14:19.33 | prpplague | crappy connection today |
| 14:19.36 | prpplague | lots of rain |
| 14:19.39 | lennert_ | 16:18 -!- prpplague [n=billybob@216.110.117.19] has quit ["Client Exiting"] |
| 14:19.46 | lennert_ | you seem to have quit yourself? |
| 14:20.11 | prpplague | lennert_: yea had to restart was getting lag |
| 14:20.21 | prpplague | lennert_: my adsl has been crappy this morning |
| 14:20.57 | prpplague | more to hit in about an hour |
| 14:51.26 | [g2] | wilma troubles ? |
| 15:17.42 | prpplague | [g2]: naw, tropical wave coming through |
| 15:17.58 | prpplague | [g2]: http://image.weather.com/images/sat/caribsat_720x486.jpg |
| 15:19.17 | prpplague | [g2]: if you follow the left side of the weather channel logo straight up you will see barbados |
| 15:19.17 | ka6sox | prpplague, as in Tsunami? Storm Surge? Cosmic Rays? |
| 15:19.18 | prpplague | [g2]: right between the two storms |
| 15:20.32 | prpplague | ka6sox: hehe i didn't make up the names, tropical wave is a description of a heavy rain that moves through an area like a waves |
| 15:22.18 | prpplague | ka6sox: http://www.weatherquests.com/services/knowledge/glossary/?code=t |
| 15:24.26 | prpplague | i had doing sdram calcs because every proc has different nomenclature for the options |
| 15:24.30 | prpplague | s/had/hate |
| 15:26.14 | ka6sox | prpplague, ah... |
| 15:51.54 | vmaster | gotta love ftdi: i told them about a deadlock problem, and they told me to add an extra delay :/ |
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| 20:27.59 | lennert_ | okay, i want to shift a 8-bit register 1 bit to the right |
| 20:28.04 | lennert_ | i did: |
| 20:28.10 | lennert_ | blah(6 downto 0) <= blah(7 downto 1); |
| 20:28.16 | lennert_ | blay(7) <= '0'; |
| 20:28.19 | lennert_ | is there any better way? |
| 20:28.41 | vmaster | that's what i found on various sites when looking for an example on how to do this |
| 20:28.58 | vmaster | a different example used a 'for' construct, iirc |
| 20:29.19 | lennert_ | 'for' will just turn into something like: |
| 20:29.23 | lennert_ | blah(6) <= blah(7); |
| 20:29.31 | lennert_ | blah(5) <= blah(6); |
| 20:29.32 | lennert_ | etc |
| 20:29.36 | lennert_ | so, that's basically the same |
| 20:29.39 | vmaster | yep |
| 20:29.47 | lennert_ | okay, thanks for your help |
| 20:32.17 | [g2] | vmaster in VHDL and Verilog all the statements in a block could happen in parallel right ? |
| 20:32.50 | lennert_ | [g2]: yeah, and they would |
| 20:33.17 | lennert_ | [g2]: so writing "a <= b; c <= a;" will load the old value of a into c |
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| 20:33.38 | lennert_ | [g2]: assuming you've clocked it |
| 20:33.44 | [g2] | yeah my qustion was about the latching of the values |
| 20:34.17 | [g2] | and if it's clocked or fully asynchronous |
| 20:34.40 | lennert_ | if you write "if clock='1' and clock'event then a <= b; end if;" then it'll be clocked |
| 20:34.56 | vmaster | what helped me understanding this is: what could the hardware look like |
| 20:35.30 | vmaster | if you clock something, there'll be a flip-flop |
| 20:35.58 | lennert_ | yeah |
| 20:36.21 | lennert_ | if you clock something and check for some other condition, it can write the flipflop's enable input with that condition |
| 20:36.30 | lennert_ | s/write/wire/ |
| 20:36.39 | vmaster | heh, yeah |
| 20:36.57 | vmaster | i learned that lesson when my gated-clock (which seemed natural to me) just broke every timing :) |
| 20:37.37 | lennert_ | my first clock divider had two processes: one process to count to 1000, and another process to output '1' if the counter was < 500 and '0' otherwise |
| 20:37.52 | lennert_ | since the < 500 comparison wasn't clocked, it broke horribly |
| 20:38.18 | lennert_ | i.e. when the counter would go from 511 to 512, it would temporarily appear as 0, and the output would go 1 even though it shouldn't have |
| 20:38.26 | vmaster | heh |
| 20:38.52 | lennert_ | i love that vhdl/verilog programming forces you to think about such issues |
| 20:40.03 | vmaster | yep, unfortunately, i have only little time now... |
| 20:40.31 | vmaster | master study is taking more time than i expected |
| 20:41.19 | lennert_ | what do you study? |
| 20:41.57 | vmaster | computer science, i've finished by diploma (4 years, between bachelor and master) a few months ago, now i'm doing a 1-year add-on for a masters degree |
| 20:43.34 | lennert_ | i'm enrolling into EE |
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| 20:46.33 | lennert_ | is there any way of building a reset generator? |
| 20:46.42 | lennert_ | is there maybe some system reset line that one can tap in some way? |
| 20:47.22 | lennert_ | (i can just assume that flipflops always initialise as zero and build a reset generator that way, but that's ugly.) |
| 20:48.21 | vmaster | on xilinx devices there's a global buffer for reset |
| 20:48.34 | lennert_ | okay, what's that called? |
| 20:48.44 | lennert_ | (if you happen to know) |
| 20:49.53 | vmaster | BUFGSR |
| 20:49.58 | vmaster | but it's no available on all devices |
| 20:50.03 | vmaster | not sure on which, the libraries guide should have it |
| 20:50.13 | lennert_ | thanks much |
| 20:57.58 | lennert_ | hey |
| 20:58.04 | lennert_ | shreg <= shref (6 downto 0) & SI; |
| 20:58.09 | lennert_ | that's a shift register |
| 20:58.17 | lennert_ | (from the xilinx xst docs) |
| 20:58.22 | lennert_ | so apparently, & is bitwise concatentation |
| 20:58.25 | lennert_ | concatenation |
| 20:58.28 | vmaster | ah, nice |
| 21:03.19 | lennert_ | the 'sll' operator is apparently shift logical left |
| 21:03.22 | lennert_ | DI <= DI sll 1; |
| 21:03.35 | lennert_ | there's also srl and rol |
| 21:04.00 | lennert_ | reading the docs is actually paying off for once :P |
| 21:05.38 | vmaster | mhh, the sxx operators wouldn't work for me |
| 21:05.49 | vmaster | not sure if i made syntax mistakes |
| 21:05.54 | lennert_ | weird |
| 21:06.18 | [g2] | test vectors are your friend right ? :) |
| 21:06.27 | [g2] | rofl |
| 21:06.47 | lennert_ | gaaaaah |
| 21:06.52 | lennert_ | elsif state = 12 and state <= 19 then |
| 21:06.57 | lennert_ | of course it doesn't work |
| 21:16.30 | vmaster | okay, i'm out - cya |
| 21:20.23 | lennert_ | cya |
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| 21:33.49 | lennert | what is a 'registered' output? a buffered output? |
| 21:36.19 | ka6sox-office | usually. |
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