| 02:22.26 | *** join/#openjtag [g2] (n=g2@nslu2-linux/g2) |
| 04:29.11 | *** join/#openjtag ByronT_ (n=byron-po@nslu2-linux/ByronT) |
| 06:23.34 | *** join/#openjtag ep1220 (n=NN@gate.epatec.at) |
| 09:47.22 | *** join/#openjtag mcdmx (n=mcdmx@84-73-8-165.dclient.hispeed.ch) |
| 15:08.41 | *** join/#openjtag vmaster (i=vmaster@p549B5B77.dip.t-dialin.net) |
| 15:14.02 | vmaster | hmm... is there anyone awake who's working on the openjtag project? i've been working on a jtag based debugger for arm systems for some time now, and i'd like to know at what point openjtag currently is - the wiki only mentions fairly general stuff |
| 15:14.49 | ep1220 | vmaster: not much done here so far. |
| 15:15.10 | ep1220 | I do have a prototype ofa FTDI2232C Jtag/USB IF |
| 15:15.21 | ep1220 | Plus basic software. |
| 15:15.24 | vmaster | heh, that's what i'm working with, too |
| 15:15.40 | ep1220 | heh |
| 15:15.55 | ep1220 | Did You do some HW/PCB ? |
| 15:16.19 | vmaster | just a prototype on a breadboard |
| 15:16.31 | vmaster | dlp2232m eval module + voltage regulator that generates 3.3v |
| 15:16.37 | ep1220 | same as me :-) |
| 15:17.24 | ep1220 | I use XScale as "victim" for tests |
| 15:17.35 | vmaster | mhh, my software supports arm7 and arm9 targets |
| 15:17.58 | vmaster | well, arm7tdmi + arm720t, no arm7-s, and arm920t |
| 15:18.26 | ep1220 | You do debugging ? |
| 15:18.26 | vmaster | but i felt a bit uncomfortable with the software i've written so far, so i decided to rewrite the whole thing |
| 15:18.29 | vmaster | yes |
| 15:18.36 | ep1220 | GDB I guess |
| 15:18.47 | vmaster | a telnet interface and a gdb interface |
| 15:18.50 | vmaster | much like bdi2000 |
| 15:19.29 | vmaster | i'm currently extending the jtag interface, to allow support for boundary scan jobs, probably a svf player |
| 15:19.46 | ep1220 | svf = ? |
| 15:19.53 | vmaster | serial vector format |
| 15:20.08 | vmaster | it's used to test boards, and to program cplds and fpgas |
| 15:20.26 | ep1220 | here we are primarily into debugging and FLASH/FPGA programming |
| 15:20.56 | ep1220 | did You roll your own SW ? or base on another project ? |
| 15:21.47 | vmaster | its written completely from scratch - i did look at jtager and arm9-jtag, but these projects had too many problems to serve as a solid base |
| 15:22.12 | vmaster | openocd.berlios.de - the page doesn't have much yet, but the latest version (alpha2) works fine for the above mentioned targets |
| 15:23.19 | ep1220 | Which license ? |
| 15:23.22 | vmaster | gpl |
| 15:24.33 | ep1220 | I was thinking GPL too, or maybe BSD |
| 15:25.11 | vmaster | i'm struggling a bit with some issues with the ftdi2232 and a fpga board with a fpga and a cpld in a daisy-chain |
| 15:25.49 | vmaster | reading the idcode using a wiggler (clone) works just fine - with the ftdi, i get bogus output |
| 15:25.59 | vmaster | works fine on my single-device arm targets though... |
| 15:26.08 | ep1220 | So far i only used it on Single device in chain, too |
| 15:26.35 | ep1220 | Did you try a lower clock ? |
| 15:26.47 | vmaster | down to a few khz |
| 15:27.47 | ep1220 | Your SW is for linux ? |
| 15:28.07 | vmaster | i was thinking about problems with the load that needs to be driven... tms and tck are shared by both devices in the chain, but i lack the electrical knowledge |
| 15:28.10 | vmaster | yes |
| 15:28.21 | vmaster | it should be fairly simple to port it to windows/cygwin |
| 15:28.31 | vmaster | but that's zero priority for me |
| 15:28.34 | ep1220 | Just asking,. as the Windows JTAG lib available from FTDI has a bug |
| 15:28.50 | ep1220 | which can give strange results. |
| 15:28.53 | vmaster | ah, ok |
| 15:29.03 | ep1220 | use libusb ? |
| 15:29.09 | vmaster | libusb + libftdi |
| 15:29.36 | vmaster | guess i'll try to get an oscilloscope |
| 15:29.58 | ep1220 | Good idea. |
| 15:30.42 | ep1220 | I am an EE. The FTDI should be able to drive 2 inputs in parallel |
| 15:31.05 | ep1220 | I did not use libftdi, but wrote my own replacement |
| 15:31.25 | ep1220 | (actually I started on Windows and then ported to Linux) |
| 15:32.13 | ep1220 | Can You elimiante the CPLD from the scan chain ? |
| 15:33.53 | vmaster | hmm, no |
| 15:34.43 | ep1220 | Which FPGA ? |
| 15:35.33 | vmaster | a xilinx virtex-2 |
| 15:36.21 | vmaster | the target is fine - my software supports wiggler-clones, too, and using it, everything is fine |
| 15:40.06 | ep1220 | I do have a SPARTAN3 board here. must check if it has 2 devices in the chain. |
| 15:40.17 | ep1220 | Then i could try reading the ID here. |
| 15:48.24 | vmaster | the ftdi datasheet mentions a high-drive mode - could that solve the problem? or would i risk damaging something? |
| 15:49.28 | vmaster | and if you're interested: http://mmd.ath.cx/thesis/ |
| 15:51.55 | *** join/#openjtag ka6sox (n=ka6sox@nslu2-linux/ka6sox) |
| 15:53.20 | ep1220 | vmaster: I be back in 20minutes |
| 15:54.54 | ka6sox | morning |
| 16:03.36 | mcdmx | morning sox... |
| 16:03.49 | mcdmx | (i mean ka6sox ;-) ) |
| 16:04.21 | mcdmx | ka6sox: did you finally get your g+? |
| 16:05.26 | *** join/#openjtag ulf_k (n=ulf_kypk@u7-67.dsl.vianetworks.de) |
| 16:07.28 | mcdmx | I'm trying to upload a kernel image to ppcboot using loadb (kermit), but after a few fragments, transmission errors occur and the transfer aborts... any hints? |
| 16:09.35 | ulf_k | with serial? |
| 16:12.26 | mcdmx | yes |
| 16:13.01 | ep1220 | vmaster: By enabling the high-drive mode you can not damage anything |
| 16:14.11 | vmaster | ah, okay, thank you |
| 16:14.16 | vmaster | i'll try that |
| 16:14.19 | ep1220 | ka6sox: morning |
| 16:14.40 | ep1220 | vmaster: Are You sure the libftdi is fully tested ? |
| 16:15.12 | ep1220 | one need to be very carefull to get the FTDI send TMS at the time one wants ;-) |
| 16:15.51 | ep1220 | vmaster: Do You have a schematic of Your FPGA/CPLD target ? |
| 16:16.12 | ep1220 | If so check if there are pull-up/down resistros on the JTAG lines. |
| 16:16.27 | ep1220 | s/resistros/resistors/ |
| 16:18.08 | vmaster | the libftdi works fine for single targets, and i've been able to download data at 25kbyte/s to an arm920t target |
| 16:18.21 | vmaster | if there were any problems, i guess i should have encountered them before |
| 16:18.27 | *** join/#openjtag [g2] (n=g2@nslu2-linux/g2) |
| 16:19.31 | vmaster | the schematics doesn't show pull-downs |
| 16:19.51 | vmaster | and no pull-ups, either |
| 16:19.59 | [g2] | heh which schematics ? |
| 16:20.18 | vmaster | a fpga/cpld dev board i'm working with |
| 16:20.37 | [g2] | excellent. what's the board going to do ? |
| 16:21.01 | ep1220 | vmaster: then likely it is not a drive problem. |
| 16:21.09 | [g2] | hey ep1220 ! |
| 16:21.26 | vmaster | [g2]: heh, nothing at the moment - i'm just using it as a target to debug my jtag code |
| 16:21.38 | [g2] | great! |
| 16:21.46 | ep1220 | vmaster: the board is on 3.3V at JTAG ? |
| 16:21.49 | ep1220 | hey [g2] |
| 16:21.51 | [g2] | I'm getting my prototype boards next week |
| 16:21.59 | ep1220 | great |
| 16:22.13 | [g2] | I'll may have a little need for some JTAG tools very soon :) |
| 16:22.38 | [g2] | Although, I've got a connector and I'll probably be able to re-flash the .5MB bootflash |
| 16:22.56 | ep1220 | vmaster: Your thesis is interesting. |
| 16:23.06 | [g2] | url ? |
| 16:23.17 | ep1220 | vmaster: Is the schematic of the FTDI complete ? |
| 16:23.18 | [g2] | sorry if I'm butting in here |
| 16:23.25 | vmaster | yes |
| 16:23.36 | [g2] | yes I'm butting in ? |
| 16:23.42 | vmaster | nah, the schematic is complete ;) |
| 16:23.52 | vmaster | [g2]: http://mmd.ath.cx/thesis/ |
| 16:23.57 | [g2] | thx |
| 16:24.14 | ep1220 | 2comments on the schematic |
| 16:24.39 | ep1220 | 1) there should be a ceramic 47 or 100nf cap from VCCIOA/B to ground. |
| 16:24.58 | ep1220 | 2) SI/WUA should not be open but at 3.3V |
| 16:25.53 | vmaster | i haven't done the board myself, just fixed some bugs my professor made... let me check this |
| 16:29.54 | vmaster | there is a 10uF capacitor to ground - is that too much? |
| 16:30.29 | vmaster | i really have only basic ee knowledge... so i'm a bit lost |
| 16:30.35 | ep1220 | vmaster: NO. that one is OK. but it's impedance is too high at higher frequencies |
| 16:30.53 | vmaster | ok, so an additional cap would be needed? |
| 16:31.05 | ep1220 | yes. in parallel to the 10uF |
| 16:31.08 | vmaster | ok |
| 16:32.15 | ep1220 | but it need to be a ceramic capacitor ! |
| 16:32.44 | ka6sox | the 10uF cap can't filter out the High Frequencies..the Ceramic does. |
| 16:33.00 | ep1220 | Do You use thru-hole or SMD ? |
| 16:33.13 | vmaster | thru-hole |
| 16:33.18 | vmaster | 0.2inch |
| 16:34.38 | [g2] | vmaster is that your masters thesis ? |
| 16:34.58 | vmaster | diploma thesis |
| 16:35.18 | ep1220 | vmaster: Your study is 3 or 5 years ? |
| 16:35.28 | vmaster | heh, 4 |
| 16:35.55 | vmaster | in germany, we used to have diploma |
| 16:36.09 | ep1220 | [g2]: then it is something between bachelor and masters |
| 16:36.10 | vmaster | they're currently transitioning to a bachelor/master scheme |
| 16:36.12 | vmaster | yeah |
| 16:36.19 | [g2] | ahh.. thx |
| 16:36.39 | [g2] | On a glance it looks very good to me |
| 16:36.40 | vmaster | i'm about to start studiying for my master in october - it's a 1-year add-on |
| 16:36.53 | [g2] | and I think you're in the right spot |
| 16:38.55 | ep1220 | vmaster: Do You have access to a digital scope or a LA? |
| 16:39.07 | vmaster | i can get one next week |
| 16:39.39 | ka6sox | vmaster, your paper is good. |
| 16:39.47 | vmaster | thx :) |
| 16:40.21 | vmaster | i saw the options you're considering as jtag hardware |
| 16:40.54 | vmaster | amontec (the chameleon dongle) is working on a usb-replacement for their paralell port chameleon, which is going to have an fpga (spartan, iirc) |
| 16:41.15 | ka6sox | the S3 board is relatively cheap but the interface takes it up too much. |
| 16:41.27 | ka6sox | the new S3e should solve this problem. |
| 16:41.57 | vmaster | ah, the one that's delayed till decemeber? |
| 16:42.00 | ka6sox | for higher performance I would still like to use the FPGA . |
| 16:42.07 | ka6sox | vmaster, yes |
| 16:42.13 | vmaster | ok |
| 16:43.14 | ep1220 | vmaster: BTW: Is Your Virtex board a commercial eval-board ? |
| 16:44.04 | vmaster | no. you can find it at fpga-dev.de |
| 16:44.17 | ka6sox | Virtex2? |
| 16:44.39 | vmaster | i got it from ebay - the person that created it sold it on ebay for 99 euros, i couldn't resist |
| 16:44.59 | vmaster | virtex2 250k gates |
| 16:46.17 | vmaster | i always wanted to play around with fpgas, and currently it's nice to have something with two devices in the jtag scan chain, to debug my code |
| 16:46.44 | ka6sox | most of my boards are 3 or more devices. |
| 16:46.53 | ka6sox | combo of FPGA/CPLD |
| 16:48.10 | vmaster | initially i started working on an ARM debugger (all targets i haved had only one device) - right now i'm rewriting the code to support multiple jtag devices, probably boundary-scan features and such |
| 16:52.49 | ep1220 | vmaster: It seems my Spartan3 has also 2 devices in the chain. |
| 16:53.03 | ep1220 | So I can try my SW too ;-) |
| 16:54.55 | vmaster | ah, yeah, would be nice to see if it works for you |
| 16:55.36 | ep1220 | I'l try on monday. |
| 16:57.22 | vmaster | hmm... i just enabled high-drive, and it seems to work |
| 16:57.45 | ep1220 | good ! |
| 16:58.23 | vmaster | yeaaah... it works :) |
| 16:58.27 | vmaster | thx ep1220 |
| 16:58.33 | ep1220 | np |
| 16:59.26 | ep1220 | actually, was your idea to enable high-drive :-) |
| 17:00.20 | vmaster | yeah, but i didn't dare to enable it, as i had no idea if that could burn my hardware |
| 17:05.29 | ep1220 | [g2]: yesterday ka6sox and I talked about making a PCB for the DLP2232M |
| 17:05.47 | ka6sox | :) |
| 17:05.59 | vmaster | amontec wanted to make one, too... haven't heard from them for a while |
| 17:06.23 | [g2] | the did the chamealon ? |
| 17:06.27 | vmaster | yes |
| 17:06.42 | vmaster | i got in contacted with them when i tried to get some information about the raven |
| 17:06.48 | [g2] | that looks like a great idea from a couple years ago |
| 17:06.54 | vmaster | heh, yeah |
| 17:07.23 | [g2] | I think we are looking to do the same except open-source the sw and make the HW way cheaper |
| 17:07.41 | [g2] | and use current generation hw not vintage stuff |
| 17:08.06 | ka6sox | the FTDI part is current tech. |
| 17:08.14 | [g2] | I got a raven the other day |
| 17:08.15 | ep1220 | I am also unsure if the FTDI is faster than a Raven |
| 17:08.27 | [g2] | someone sent me one free |
| 17:08.35 | [g2] | along with a NIOS kit |
| 17:08.50 | vmaster | hmm, i achieved around 12kb/s ram download with the raven |
| 17:08.54 | ep1220 | seems I know the wrong people :-( |
| 17:09.03 | vmaster | compared to 25kb/s using the ftdi2232 |
| 17:09.09 | vmaster | kbyte |
| 17:09.28 | [g2] | vmaster do you vhdl/verilog ? |
| 17:09.54 | vmaster | no, but i plan on learning it - haven't done anything with it yet |
| 17:10.40 | [g2] | do you know what those Virtex II boards cost ? |
| 17:11.07 | vmaster | i bought mine for 99 euros, but the five boards he sold on ebay were the last ones, i guess |
| 17:11.23 | vmaster | the virtex 2 is ~150$ alone |
| 17:11.26 | [g2] | is there a new design planned ? |
| 17:11.50 | vmaster | i don't know - i saw it on ebay, sent him the money, and got my board on tuesday |
| 17:11.57 | [g2] | heh |
| 17:13.06 | [g2] | well I'm really ready to get things rolling |
| 17:13.24 | [g2] | ep1220 has been a great driver |
| 17:13.41 | [g2] | my hat's off to him for all his great work |
| 17:14.05 | ep1220 | to much honor |
| 17:14.12 | ep1220 | s/to/too/ |
| 17:14.20 | [g2] | however, I see at least 3 major needs in the near future |
| 17:14.48 | [g2] | One .. I want to be able to ship real cheap hardware with my board which comes with a jtag header |
| 17:15.05 | vmaster | real cheap == wiggler clone |
| 17:15.32 | [g2] | two .. The NSLU2s really need cheap easy JTAG bootloader testing |
| 17:15.50 | vmaster | mhh, what's the NSLU2? |
| 17:16.00 | [g2] | three ... The Linksys RV series has a 20 pin JTAG layout... |
| 17:16.20 | ka6sox | vmaster, its a NAS box that we have been hacking on for a year |
| 17:16.23 | [g2] | I'd like to start seriously hacking those boards after the Loft is up and running |
| 17:17.00 | [g2] | the NSLU2, Loft and Linksys Rv boxen are all IXP4xx base Xscale |
| 17:17.26 | [g2] | IXP420, IXP422 and IXP425 to be exact |
| 17:18.05 | vmaster | ah, nice |
| 17:18.06 | ka6sox | 425 has a VPN engine? |
| 17:18.10 | vmaster | USB2.0 to Ethernet? |
| 17:18.13 | vmaster | cool |
| 17:18.44 | [g2] | the Loft as the 422 that's got the crypto hw too |
| 17:18.50 | [g2] | Loft has |
| 17:19.50 | ka6sox | very nice |
| 17:22.36 | ep1220 | [g2]: the FTDI will not meet your need one |
| 17:23.21 | [g2] | ep1220 I'm interested in the FTDI but it's kinda a middle ground |
| 17:23.44 | [g2] | If we can build it pretty cheaply then I'd use that |
| 17:24.18 | [g2] | But we can buy cheap wigglers from digilent for like $12 bucks |
| 17:24.30 | [g2] | I haven't played with the USB version which is $19 |
| 17:25.59 | ep1220 | the digilent USB does not give You reset and TRST |
| 17:26.08 | ep1220 | but is OK for FLASH programming |
| 17:27.09 | ep1220 | [g2]: unless You go for a few hundred units the FTDI will not come below 60-70$ |
| 17:27.23 | ka6sox | ep1220, I still like the idea of using the icache to program the flash in a Xscale :) |
| 17:28.14 | ep1220 | this will give You great performance. but need HW which controls reset and TRST |
| 17:28.32 | [g2] | ep1220 at those prices it just makes sense to go with an S3 build or just buy S3 dev boards |
| 17:29.14 | ep1220 | g2: disagree. the S3 dev board plus USB is 200$ |
| 17:29.45 | ep1220 | And this is no yet a JTAG |
| 17:30.15 | vmaster | does anyone know what is "inside" the digilent usb part? |
| 17:30.27 | ep1220 | a cypress USB2 chip |
| 17:31.21 | vmaster | nice |
| 17:32.25 | ep1220 | g2: there are other costs, like a USB vendor ID is 1500$ |
| 17:32.29 | [g2] | ep1220, I've been told that an S3 can drive line rate JTAG (10 Mbs scan change) via a parallel adapter |
| 17:32.44 | [g2] | it makes sense to me |
| 17:33.03 | ep1220 | You mean connect to the parallel port ? |
| 17:33.22 | [g2] | I'm saying the host connection isn't the limiting rate |
| 17:33.45 | [g2] | and the new S3 board has ethernet memory on board for $150 |
| 17:33.58 | ep1220 | I did some eval on S3, I can do 40-70Mhz ;-) |
| 17:34.15 | [g2] | on the scan chain ? |
| 17:34.20 | ep1220 | yes. |
| 17:34.26 | [g2] | right.... |
| 17:34.42 | [g2] | so the limiting issues in my mind are: |
| 17:34.45 | ep1220 | g2: but you still need JTAG headers |
| 17:34.47 | [g2] | 1) The FPGA programming |
| 17:34.57 | [g2] | 2) the interface to the host |
| 17:35.17 | ulf_k | hi |
| 17:35.20 | ep1220 | agree |
| 17:35.38 | [g2] | short term I may have some minor issues with JTAG |
| 17:35.53 | [g2] | my case with the Loft is pretty straight forward |
| 17:36.50 | ulf_k | after some week without success i stoped working on jtaging the ixp425 based board. |
| 17:36.59 | [g2] | I've got 4Mb part which is only .5MB |
| 17:37.09 | [g2] | so I don't have a ton of reprogramming to do |
| 17:37.30 | [g2] | Redboot it probably already ported and working on the board |
| 17:37.37 | [g2] | s/it/is/ |
| 17:38.01 | [g2] | However, this is a *very* important item long-term open development |
| 17:38.12 | [g2] | and a "brick-free" envirionment |
| 17:38.53 | [g2] | ulf_k thanks for hanging around |
| 17:39.20 | ulf_k | you are very welcome |
| 17:41.04 | [g2] | ulf_k you just need a flash programming update |
| 17:41.54 | ulf_k | how you meen update? i can maybe work on a very expencive windows tool for example |
| 17:42.27 | [g2] | I mean you need the flash programming algorithms updated for the JTAG tool |
| 17:42.42 | ulf_k | ahh yes |
| 17:42.49 | [g2] | or you need to just download a small program to memory |
| 17:43.15 | [g2] | It might be easy for someone like ep1220 or vmaster to update the jtag tools to allow memory writes |
| 17:43.28 | [g2] | then we'd be able to download programs to the memory |
| 17:43.35 | ulf_k | well my openjtag is not able to write mem |
| 17:43.46 | ulf_k | i saw a patch for it in the cvs |
| 17:43.51 | [g2] | that's the capability I'm talking about use adding |
| 17:44.01 | [g2] | s/use/us/ |
| 17:44.10 | [g2] | if it's in CVS then all the better |
| 17:44.26 | [g2] | we should sign up for the jtag ML or get on the forum |
| 17:45.24 | ulf_k | one big question i have, can you look on this website, there are 3 ways of plugs, the 14 and 20 pin, i know, but also one 8 pin version, here the link: |
| 17:45.28 | ulf_k | http://hri.sourceforge.net/tools/jtag_faq_org.html |
| 17:46.36 | ulf_k | ok my board has a not printed 20 pin jtag i put that plugs on it and tried all the time, now i saw that there is one factory made 8 pin plug |
| 17:47.16 | ulf_k | the same as shown in the faq, with one missing an 5 |
| 17:50.12 | ulf_k | so my question what is pld programming? |
| 17:50.42 | ep1220 | pld = Programmable logic device (AKA: PAL;GAL;CPLD;FPGA;..) |
| 17:52.01 | ulf_k | do i need for this a special connector or can i use the wiggler adapter |
| 17:55.00 | vmaster | [19:43] < [g2]> It might be easy for someone like ep1220 or vmaster to update the jtag tools to allow memory writes |
| 17:55.07 | vmaster | memory writes for xscale? |
| 17:55.13 | [g2] | nod |
| 17:55.31 | [g2] | ep1220 has written to the mini-I cache and booted off it |
| 17:55.56 | [g2] | that's a significant milestone in my book |
| 17:56.04 | vmaster | yeah |
| 17:56.12 | vmaster | xscale debugging is somewhat different from other ARMs |
| 17:56.30 | [g2] | If we just added loading the mini-I cache or the full I-cache we could load a bootloader with serial and boot it |
| 17:56.35 | [g2] | APEX for example |
| 17:57.02 | [g2] | We'd only need to bring up serial, memory, and the ability to flash |
| 17:57.17 | vmaster | do you know "jeelie"? |
| 17:57.32 | [g2] | actually... just serial and memory as we could download additional code and run it over the serial |
| 17:57.45 | [g2] | don't know jeelie |
| 17:57.49 | [g2] | should I ? |
| 17:58.00 | [g2] | Do you know bewoolie ? |
| 17:58.04 | [g2] | beewoolie ? |
| 17:58.19 | vmaster | ah, jelie |
| 17:58.21 | vmaster | http://lap.epfl.ch/dev/arm/jelie/ |
| 17:58.30 | [g2] | http://wiki.buici.com/twiki/bin/view/Main/ApexBootloader#IXP42x_and_the_Linksys_NSLU2_aka |
| 17:58.32 | vmaster | an open source xscale jtag debugger |
| 17:58.51 | [g2] | that's sounds very nice :) |
| 17:59.11 | ep1220 | g2: JMunakra mentioned this one some time ago |
| 17:59.46 | ep1220 | they use the ezUSB |
| 18:01.16 | [g2] | great so using jellie with a wiggler would work assuming IXP4xx hardware is supported |
| 18:01.25 | vmaster | it is not |
| 18:01.55 | vmaster | but as they're both xscale, it shouldn't require too much to get it work |
| 18:02.13 | [g2] | exactly :) |
| 18:26.34 | ulf_k | pld programming: does this strange little chip called "lattice lc4032v" has something to do with this? |
| 18:28.39 | ep1220 | yes. this is a CPLD |
| 18:28.50 | ulf_k | aha ok |
| 18:29.21 | ulf_k | can you tell me a bit more about, please? |
| 18:30.52 | ep1220 | Do You have a schematic of the board You are using ? |
| 18:31.57 | ulf_k | i can send you a picture, i am still working on a final infopage with all this stuff |
| 18:33.10 | ep1220 | picture of the PCB ? |
| 18:39.03 | *** join/#openjtag ulf_k_ (n=ulf_kypk@u7-67.dsl.vianetworks.de) |
| 18:39.49 | ulf_k_ | stupid 24h reconnect from provider |
| 18:40.27 | ulf_k_ | i hate this, i have to set a cron to reconnect at 7 in morning |
| 18:41.15 | ka6sox | what TZ are you in ulf? |
| 18:41.30 | ulf_k_ | well ep1220 what is a PCB? |
| 18:41.45 | ka6sox | circuit board |
| 18:42.23 | ulf_k_ | ohh all your shortcuts i guess timezone, haha germany |
| 18:43.08 | vmaster | CEST |
| 18:43.31 | ka6sox | okay...didnt' htink it was 7am in CEST |
| 18:43.56 | ep1220 | it is not :-) |
| 18:44.05 | ep1220 | it is 8:46pm |
| 18:44.09 | ulf_k_ | here its 8pm |
| 18:44.29 | vmaster | CEST is eastern timezone +6h, iirc |
| 18:45.13 | ka6sox | oh...wait. |
| 18:45.15 | ulf_k_ | you are all from us? |
| 18:45.36 | ka6sox | I am GMT -8 |
| 18:45.52 | vmaster | ok, CEST is GMT+1 |
| 18:46.07 | ka6sox | yes |
| 18:46.16 | ulf_k_ | by the way, is it allowed to present pdf file from the fcc on a own website for information? |
| 18:46.54 | ka6sox | the FCC database is supposed to be public domain |
| 18:47.02 | ka6sox | but not always. |
| 18:47.26 | ka6sox | there *might* be somethings that they keep but you shouldn't be able to get anything from there that isnt' public. |
| 18:47.45 | ka6sox | I'm assuming you mean Federal Communications Commission. |
| 18:47.58 | ulf_k_ | yes |
| 18:48.13 | ulf_k_ | the pdfs are public |
| 18:48.20 | ulf_k_ | on the fcc website |
| 18:48.30 | ka6sox | are you looking at a circuit board picture? |
| 18:48.57 | ulf_k_ | well the circuit board picture i made by my self |
| 18:49.21 | ka6sox | is that posted somewhere? |
| 18:49.29 | ulf_k_ | but the wireless cards on this device are shown in some pdfs from dlink on the fcc website |
| 18:49.51 | vmaster | ulf_k_: if the pdf is public on the fcc site, put a link to the original location on your page - that way you're on the safe side |
| 18:50.19 | ka6sox | good plan |
| 18:50.48 | ulf_k_ | yes normaly but now you can not find this fcc site any more |
| 18:51.05 | ulf_k_ | archive.org maybe |
| 18:51.05 | ka6sox | what was the pdf of? |
| 18:52.49 | ulf_k_ | ok, give me about an hour to setup all this, i am still weeks sitting here and thinking of putting all this on my website |
| 18:53.09 | ka6sox | k |
| 18:54.17 | ulf_k_ | but first a cool beer, you have to know since 2 days im in my new office, the old was attacked from the rats ;) |
| 18:55.03 | [g2] | ulf_k_ where is your web site ? |
| 18:55.07 | ulf_k_ | and im so happy to finish the old office story after 3 years |
| 18:55.08 | [g2] | as in URL ? |
| 18:57.06 | ep1220 | ka6sox: back to FTDI ;-) |
| 18:57.06 | ulf_k_ | about my project http://www.wlanhain.de but its not updated since half a year, and it is in german only, but my girlfriend translated it already, she is from the states |
| 18:57.41 | ep1220 | I plan to add serial and level-converters |
| 18:57.55 | ep1220 | maybe 4 GPIO pins (?) |
| 18:58.08 | ka6sox | okay...is that in addition to the SSE stuff? |
| 18:58.13 | ep1220 | yes |
| 18:58.39 | ka6sox | multi headed hydra....cool |
| 18:58.59 | ep1220 | serial is 3.3V only (?) |
| 18:59.04 | ka6sox | that would be a useful tool. |
| 18:59.12 | ep1220 | JTAG is 1.2 to 3.3V |
| 18:59.12 | ka6sox | I think so. |
| 18:59.44 | ep1220 | (?)was more: do you need another voltage as well ? |
| 19:00.21 | ka6sox | 3.3v serial (before level shifters) is very good. |
| 19:00.26 | ka6sox | 5v is unnecesary |
| 19:00.58 | ep1220 | I did not plan level-shifters on the serial (RS232) |
| 19:01.14 | ka6sox | k |
| 19:01.20 | ka6sox | then 3.3v is still good. |
| 19:02.04 | ep1220 | 5V on JTAG is an issue for You ? For anyone else listening. |
| 19:02.35 | ka6sox | trying to remember if I have anything that uses 5v jtag |
| 19:06.38 | ep1220 | open point: Which JTAG header ? 14, 20pins ? ARM, MIPS,.. More than one ? |
| 19:06.48 | ka6sox | more than one |
| 19:07.03 | ka6sox | 7 digilent 14 and 20 would be nice. |
| 19:07.38 | ulf_k_ | have you seen the faq from hri |
| 19:07.45 | ulf_k_ | http://hri.sourceforge.net/tools/jtag_faq_org.html |
| 19:08.03 | ulf_k_ | the hri project is great |
| 19:09.22 | ep1220 | ulf_k_: Thx for the URL |
| 19:10.03 | ulf_k_ | you are welcome |
| 19:10.11 | ep1220 | ka6sox: I think i try to use thru-hole parts wherever possible. |
| 19:10.22 | ep1220 | guess, size is not so important. |
| 19:10.22 | ka6sox | sounds easy to build. |
| 19:11.14 | ep1220 | right, so everyone who does not want to pay for building can do it himself |
| 19:22.22 | ka6sox | very ince |
| 19:23.01 | ka6sox | er nice |
| 19:23.42 | ka6sox | I'll buy a couple of blank boards...:) |
| 19:24.32 | ep1220 | :-) |
| 20:50.21 | *** part/#openjtag ep1220 (n=NN@gate.epatec.at) |
| 22:54.01 | ulf_k_ | someone stiff awake? |
| 22:54.29 | vmaster | yeah |
| 22:56.42 | *** part/#openjtag mcdmx (n=mcdmx@84-73-8-165.dclient.hispeed.ch) |
| 23:02.04 | ulf_k_ | i an finished with updating website and put a picture from the xscale based accesspoint dwl-7000 |
| 23:02.17 | ulf_k_ | here the link: http://www.wlanhain.de/morewireless/hardware/dwl-7000/ |
| 23:05.59 | vmaster | ok, and what was your question regarding this? |
| 23:09.29 | ulf_k_ | some days ago i had a conversation with g2 about my jtag problem on this board, i use the 20pin jtag, yesterday i saw on the jtag faq website from hri 3 ways of jtag 14 pin 20 pin or 8pin for pld |
| 23:10.14 | ulf_k_ | and this board has a lattice CPLD |
| 23:10.19 | vmaster | yeah |
| 23:10.38 | vmaster | the 8-bit header is the lattice isp layout |
| 23:10.50 | ulf_k_ | so how do i use the 8 pin interface with what kind of hardware and what kind of tools? |
| 23:11.53 | ulf_k_ | i guess this is different to the 20 pin jtag with wiggler adapter i use with my parallelport |
| 23:12.12 | vmaster | what do you want to do? do you want to program the pld? or do you want to work with the processor? |
| 23:12.32 | vmaster | the signals are more or less the same, on the 20 pin header |
| 23:12.37 | ulf_k_ | i what to write to the flash |
| 23:13.08 | vmaster | ok, the signals are almost the same |
| 23:13.26 | vmaster | the 20-pin arm header has reset signals that the 8-pin header misses |
| 23:13.45 | ulf_k_ | so d i use still my wiggler adapter? |
| 23:14.15 | vmaster | it depends on how the components are wired on the board |
| 23:14.21 | vmaster | jtag devices can be put in a chain |
| 23:14.47 | ka6sox | vmaster, yes but a lot of things have the digilent connector. |
| 23:14.52 | ka6sox | so it should be included ;) |
| 23:15.45 | vmaster | included where? |
| 23:16.32 | vmaster | ulf_k_: www.intel.com/design/iio/ devtools/iq80310/lattice_ispdownload.pdf that's the layout of the lattice header |
| 23:19.31 | vmaster | and there's the layout of the embedded-ice connector (20-pin): http://www.arm.com/support/Embedded-ICE%20Adaptor%20Schematic.pdf |
| 23:23.23 | ulf_k_ | sorry i don't understand all this :( i will make i little summary: i use a selfmade par port adapter to 20 ping jtag and use jtag from openwince to access to the board, this works somehow, because i get infos back from the board when givving the command detect and detectflash 0, so far so good but i can not write maybe read as well i do not really know |
| 23:25.12 | vmaster | ah, okay |
| 23:27.47 | ka6sox | oh..niever mind... |
| 23:31.29 | ulf_k_ | so this strange errors i get while flashing written stuff is comparing from the original i have continuous parts where f's written instead of real content |
| 23:33.15 | ulf_k_ | and how the other connection possibility can maybe work without this errors while writing to the flash, so what should i do now, can i just plug my jtag adapter in the correct pin layout to the 8 ping plug instead of the 20 pin plug |
| 23:33.21 | vmaster | an erased flash is all ones, so continous parts with only ffs is an erased region |
| 23:33.59 | vmaster | this isn't a matter of the jtag connection, if the jtag tools were able to identify the chip and the flash |
| 23:34.46 | ulf_k_ | well the the flash chip is not really supported |
| 23:35.05 | ulf_k_ | it is a am29lv320 and only 160 and 640 are supported |
| 23:35.31 | ulf_k_ | but erasing, and reading are passible |
| 23:36.57 | ulf_k_ | when reading some parts from the flash it is correct i hope, at least there are no continuous parts with fff |
| 23:39.38 | ulf_k_ | ka6sox: have you seen the dwl7000 picture |
| 23:41.29 | vmaster | ulf_k_: it's likely that you'll have to change the code in amd.c to match your flash chip |