| 02:42.12 | *** join/#openjtag ka6sox (n=ka6sox@nslu2-linux/ka6sox) |
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| 06:21.29 | pinke | nobody online? |
| 06:21.48 | ka6sox | sorta...1/2 asleep! |
| 06:23.42 | pinke | hehe. |
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| 06:28.08 | pinke | zZ^~~~~~ ,who can tell me witch framework easy to learn and usefulness ? |
| 06:29.03 | ka6sox | I really am 1/2 asleep...framework? |
| 06:29.16 | ka6sox | vhdl/verilog or something else? |
| 06:30.57 | pinke | ^O^m,,,,where can found samething about these ?? |
| 06:31.50 | ka6sox | they are both useful for lowlevel work with FPGA's and CPLD's |
| 06:33.39 | pinke | TKS.. |
| 06:33.44 | ka6sox | np! |
| 06:34.00 | ka6sox | googling for VHDL or Verilog tutorial will telll you! |
| 06:34.21 | pinke | OK, |
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