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| 11:28.15 | JMunakra | What is the current development status of JTAG adapter hardware? |
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| 15:38.21 | JMunakra1 | What is the current development status of JTAG adapter hardware? |
| 15:56.54 | Tiersten | The hardware is pretty much standardised on the Spartan 3 devboard. Progress is a bit slow at the moment because all the developers are busy with other projects. |
| 16:00.35 | JMunakra1 | is ep working on it? |
| 16:03.31 | Tiersten | Don't know. Why? |
| 16:04.54 | JMunakra1 | I'm interested in the details |
| 16:06.40 | Tiersten | Okay. There are two choices for platform at the moment. A FPGA or a FTDI USB dongle |
| 16:07.07 | JMunakra1 | yup |
| 16:07.17 | Tiersten | The FPGA being more powerful but also harder for other people to develop on since it requires knowledge of VHDL |
| 16:07.39 | Tiersten | The USB one being easier since most of it will be running on the host PC |
| 16:07.51 | JMunakra1 | And I gathered that work is being done on the FPGA |
| 16:07.58 | Tiersten | We're investigating both |
| 16:08.50 | Tiersten | However, as I said earlier we're all pretty busy. Most of us are also on the NSLU2-Linux project and that is requiring a lot of time at the moment |
| 16:31.05 | JMunakra1 | Hm, I have a problem with the openjtag wiki |
| 16:31.17 | JMunakra1 | do I always need \\ for a line break? |
| 16:31.34 | JMunakra1 | without, all the lines are concatenated |
| 16:31.46 | JMunakra1 | that seems stupid |
| 16:32.07 | Tiersten | That's normal |
| 16:32.18 | Tiersten | Put it into paragraphs with a line in between if you don't want that |
| 16:34.00 | JMunakra1 | but then I get paragraphs |
| 16:34.54 | Tiersten | You have to put the \\'s in otherwise it thinks you want paragraphs |
| 16:35.15 | Tiersten | It's the same way HTML works for formatting except it uses \\ instead of <br> |
| 16:35.33 | JMunakra1 | is it the mediawiki engine? |
| 16:35.38 | Tiersten | No. pmwiki |
| 16:35.52 | JMunakra1 | oh, I was used to mediawiki |
| 16:40.23 | JMunakra1 | Does the wiki allow hierarchical grouping like 1.1, 1.2, 1.2.1, 1.3 etc.? |
| 16:40.44 | Tiersten | It doesn't handle sections. You can do numbered lists if you wish but that's it |
| 17:12.45 | JMunakra1 | OK, I updated the wiki to reflect the options that were being evaluated. |
| 17:17.02 | Tiersten | Thanks. Are you interesting in the debugging aspect or the flash rewriting part? |
| 17:18.02 | JMunakra1 | More in the debugging, but it goes hand in hand IMHO |
| 17:18.31 | Tiersten | k. Just wondering. Some people just want to be able to reflash stuff quickly since the only free or very low cost adapters out there are incredibly slow |
| 17:18.34 | JMunakra1 | I have my own JTAG library, but I'm missing hardware, so I'm most interested in hardware! |
| 17:18.45 | Tiersten | 100 bytes per second for a parallel port dongle doing a XScale |
| 17:18.46 | Tiersten | Oh? |
| 17:20.50 | JMunakra1 | I wanted to help making the FPGA core, but I don't have a PC right now, and I can't run the synthesis tools on my Mac :) |
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| 17:23.26 | Tiersten | VirtualPC? :) |
| 17:23.47 | JMunakra1 | qemu, it is SLOOOW |
| 17:24.43 | Tiersten | We're not supporting the Linux tools at the moment. Last time one of us tried it, the bitstream generated was really wacky |
| 17:25.13 | Tiersten | It was wrong and totally different to what the Windows tools synthesized |
| 17:25.36 | JMunakra1 | argh :) We love xilinx |
| 17:26.16 | Tiersten | It *may* be better now. We've not tested it. I hope it's better anyway... |
| 17:26.28 | Tiersten | The last time it was tested, the Linux tools were still non free |
| 17:27.03 | JMunakra1 | the WebPack? |
| 17:28.38 | Tiersten | Yeah. They didn't have that then for Linux |
| 17:29.00 | JMunakra1 | but that was a LONG time ago |
| 17:29.16 | Tiersten | Yep |
| 17:29.30 | Tiersten | As I said, hopefully it works now :) |
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| 21:32.58 | JMunakra | hey g2 |
| 21:34.04 | [g2] | JMunakra, howdy! |
| 21:34.15 | JMunakra | I updated the wiki :) |
| 21:34.34 | JMunakra | I added some initial text on the JTAG hardware being discussed |
| 21:34.42 | JMunakra | but that info is 2 months old |
| 21:34.56 | JMunakra | so if there's news to that.... have a look and tell me |
| 21:35.23 | [g2] | ep1220 has made great progress with the FTDI and then NSLU2 |
| 21:35.33 | [g2] | FTDI chip hooked up to the NSLU2 |
| 21:35.51 | JMunakra | Is he using the EZNIOSUSB? |
| 21:36.04 | [g2] | he's been able to JTAG load directly into the mini-I cache and execute code |
| 21:36.18 | [g2] | No I think it's just a chip on a eval board |
| 21:36.34 | JMunakra | is there a link for it |
| 21:38.17 | [g2] | check with ep1220 |
| 21:38.39 | [g2] | He'll be moving on the the Spartan3 FPGA implementation in a little while |
| 21:38.57 | [g2] | but he's verfied that the JTAG is working with the FTDI eval board |
| 21:39.30 | JMunakra | sounds good |
| 21:39.35 | JMunakra | is the code in CVS? |
| 21:41.02 | [g2] | I don't think so |
| 21:41.13 | [g2] | I don't know what ep1220's plans are for it |
| 21:41.22 | [g2] | but that's a good question |
| 21:41.57 | JMunakra | I'd like to have a look at it for sure :) |
| 21:42.29 | [g2] | last week we resolved the mystery about whether the nslu2 runs at 133 or 266 |
| 21:42.50 | JMunakra | and? |
| 21:43.15 | NAiL | It's brilliant : |
| 21:43.17 | NAiL | :D |
| 21:43.36 | [g2] | it runs at 133 but .... http://www.nslu2-linux.org/wiki/HowTo/OverClockTheSlug |
| 21:43.39 | NAiL | [g2] :) |
| 21:44.02 | [g2] | NAiL, what's brilliant ? |
| 21:44.19 | NAiL | the mod :) |
| 21:44.28 | [g2] | yes. |
| 21:44.40 | JMunakra | It'll get warm. |
| 21:44.56 | [g2] | JMunakra, what will get warm ? |
| 21:45.03 | JMunakra | just reading |
| 21:45.41 | [g2] | DOH! sorry s/it/he/ |
| 21:45.45 | NAiL | haha |
| 21:45.55 | [g2] | that's *not* funny :( |
| 21:46.20 | JMunakra | so you have the xscale docs, and they didn't document those pins? |
| 21:46.50 | NAiL | [g2]: sry |
| 21:47.32 | [g2] | Linksys uses an undocumented feature do under clock the device to 1/2 it's lowest speed grade which is 266 |
| 21:48.04 | JMunakra | what crystal freq do they have? |
| 21:48.59 | [g2] | 33 |
| 21:49.40 | JMunakra | hm, so they have a couple of DLLs in there, and can skip one |
| 21:52.07 | [g2] | DPLL ? |
| 21:53.43 | JMunakra | DLL = delay locked loop |
| 21:54.23 | [g2] | ok... I'm not sure about DLL |
| 21:54.44 | [g2] | I know about Phase locked loops and Digital Phase Locked loops |
| 21:54.47 | JMunakra | me neither, but that's what FPGAs use to double clocks |
| 21:55.06 | [g2] | it think we're saying the same thing |
| 21:55.20 | JMunakra | there must me a slight diferrence though |
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