irclog2html for #openjtag on 20050628

00:43.49*** join/#openjtag NAiL (~repvik@84.16.208.26)
01:53.59*** join/#openjtag ByronT-Away (~byron-por@ByronT.nslu2-linux)
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12:01.54*** join/#openjtag prpplague (~billybob@216.110.99.130)
15:06.09*** join/#openjtag ep1220 (~NN@gate.epatec.at)
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16:15.06[g2]ep1220, pnig
16:15.09[g2]ep1220, ping
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17:54.03*** join/#openjtag Tiersten (tman@Tiersten.nslu2-linux)
18:11.00ep1220[g2] am here now
18:11.19[g2]ep1220, hey !
18:11.24ep1220hey
18:11.41[g2]The NSLU2 appears to be running at 133 MIPs
18:11.58ep1220shouldn#t it be 266 ?
18:12.07[g2]it should be but doesn't appear to be
18:12.19[g2]this has been brought up before
18:12.40[g2][g2]> Microseconds for one run through Dhrystone:     5.8
18:12.40[g2]<[g2]> Dhrystones per Second:                        172176.3
18:12.40[g2]<[g2]> VAX MIPS rating =     97.994
18:12.56[g2]that's on the NSLU2 which shows 133 BogoMIPS
18:13.12[g2]Microseconds for one run through Dhrystone:     2.9
18:13.12[g2]<[g2]> Dhrystones per Second:                        350140.1
18:13.12[g2]<[g2]> VAX MIPS rating =    199.283
18:13.41[g2]That's on my avila board which is an IXP422 @ 266 and shows 266 BogoMIPS
18:13.54jacques[g2], wallclock time on the avila should be about 10 seconds
18:14.37jacques:-)
18:14.55jacquesoh, and make sure your wallclock isn't running at double speed
18:15.05[g2]nod :)
18:15.06jacquesor half speed
18:15.45ep1220Do the Avila and NSLU2 use same number of wait-states on RAM ?
18:16.13jacquesdoes that even matter for dhrystone?
18:16.33ep1220Do not know
18:18.57[g2]ok 14 seconds wall clock
18:19.13[g2]real    0m 14.83s
18:19.13[g2]user    0m 14.28s
18:20.27jacques[g2], that's for 5,000,000 iterations?
18:21.03[g2]Dhrystones per Second:                        175192.7
18:21.03[g2]VAX MIPS rating =     99.711
18:21.03[g2]real    0m 28.55s
18:21.10[g2]avila versus slug
18:21.36[g2]Dhrystones per Second:                        175192.7
18:21.36[g2]VAX MIPS rating =     99.711
18:21.36[g2]real    0m 28.55s
18:21.49jacquesI get almost exactly 30 seconds on a slug
18:22.05[g2]echo '5000000' | time ./dhry2
18:22.16[g2]well this is a fatslug :)
18:23.19jacqueswell, according to pb, using the device's clock makes the results suspect which is why I kept saying wallclock time
18:23.48[g2]VAX MIPS rating =    199.283
18:23.56[g2]NOD that's a good thing to check
18:24.07[g2]but in this case wall clock == onboard clock
18:24.38jacquesanyway, I think we've shown that the avila is twice as fast at dhrystone
18:24.58[g2]nod
18:25.02[g2]wall time
18:25.25jacquestwice as fast
18:25.38jacquesit does 2x as many iterations in the same amount of time
18:25.45[g2]I was wonder if ep1220 or Tiersten had a scope and could output a clock to a GPIO or measure the PCI clock
18:25.57[g2]right
18:26.15[g2]I'll run 10,000,000 iterations in 28 secs
18:26.31ep1220[g2] I do have a scope (200MHz BW) and a 200mHz LA
18:26.31jacquesman it sure would suck if they had to lower the speed because of some pci/usb controller instability
18:26.52ep1220Hehe, the LA is 200MHz
18:27.03[g2]lucky bastard! :)
18:27.31jacquesbut it sure would be sweet if we can suddenly get full 100TX TCP saturation and 20MB/s USB
18:27.34[g2]but I've got a board the runs faster :)
18:28.01ep1220[g2]: could it be there are IRQs running during the benchmark ?
18:28.03[g2]jacques, the current using does 100TX TCP saturation
18:28.48[g2]s/using/unit/
18:31.29jacquesok fine
18:31.36[g2]thttpd will saturate the line at 100Mbs for < 30MB files
18:31.56jacqueshmm
18:32.07jacquesdoesn't that use UDP packets?
18:32.23[g2]http
18:32.31[g2]TCP port 80 thingy
18:32.38jacquesoh, ok thought you said tftpd
18:32.47[g2]now thttpd
18:32.53[g2]now
18:32.55[g2]no
18:38.36[g2]ep1220, they are pretty much running the same sw
18:39.07[g2]there is not RTC on the avila
18:39.13[g2]no
18:39.23ep1220[g2]: Do You run the benchmark directly from the bootloader ?
18:39.30ep1220Or under an OS ?
18:39.36[g2]from Linux
18:39.44[g2]statically linked
18:40.01[g2]I can reboot the slug and run it from flash like the avila
18:40.45ep1220so the avila has no Linux during benchmark ?
18:41.03[g2]they both are run from linux
18:41.17[g2]the nslu was from external hd with swap
18:41.41[g2]now it's from jffs2 like the avila
18:43.21[g2]from jffs2
18:43.24[g2]VAX MIPS rating =     99.572
18:43.24[g2]real    0m 29.33s
18:43.29[g2]same as disk
18:45.35ep1220The devManual says the UART clock is derived from the system clock
18:46.00ep1220So if the same divisor gives same baud-rate the core-clocks must be identical
18:48.35[g2]that makes sense, but something is accounting for the difference
18:49.39ep1220can you run the benchmark without linux under it ?
18:49.57[g2]no it's linux program
18:51.16ep1220CMIIAW, but dryhstone should not use OS calls (?)
18:51.54[g2]CMIIAW ?
18:52.06ep1220Correct me if I am wrong
18:52.52[g2]it'd imagine it gets in a tight looop
18:55.39jacquesdhrystone uses the libc string functions heavily
18:56.14ep1220But these should not call into Linux (?)
18:56.22jacquesyou mean the kernel ?
18:56.24ep1220yes
18:56.50*** join/#openjtag beewoolie-afk (~beewoolie@florence.buici.com)
18:56.58jacqueswell it has to access the console to display the results
18:57.13jacquesep1220, but what is your point?
18:57.16beewoolie-afkHey folks
18:57.21[g2]beewoolie-afk, hey!
18:57.30jacquesare you saying that because the dhrystone benchmark runs under an OS it's somehow not valid ?
18:57.47[g2]beewoolie-afk, how's the MAN!
18:57.59ep1220jacques: No i mean maybe the OS (or a driver) steals some time
18:58.16ep1220e. an IRQ could invalidate the cache
19:00.48jacquesho wlikely is it that it would cause the benchmark to be almost exactly 1/2 ?
19:01.14jacquesand what about the kernel computing bogomips? I don't think the OS would be stealing time at that point
19:01.42ep1220Do not know how bogomips are implemented.
19:04.32ep1220the Wiki says: GPIO14 and 15 are (should eb) both 33Mhz clocks
19:05.01ep1220maybe i find an "access point" at one of these nets.
19:05.06jacques:-)
19:06.59[g2]ep1220, that'd be great
19:07.23[g2]you know about the detailed picturres on the wiki right ?
19:07.31beewoolie-afkBogomips are called bogo for a reason.
19:08.18prpplaguebeewoolie-afk: hey
19:08.21prpplaguebeewoolie-afk: whats cookin
19:08.50beewoolie-afkprpplague: been on the Cisco router & IPv6 research train.
19:08.52jacquesman if I hear that one more time
19:09.01jacquesabout bogomips
19:09.33beewoolie-afk;-)
19:09.45ep1220g2: now I now.
19:09.46[g2]beewoolie-afk, we've run a drystone benchmark on the avila and nslu2 and it comes out 2x on the avila
19:09.57[g2]now I know ?
19:10.12beewoolie-afkThat makes sense.
19:11.03[g2]beewoolie-afk, they are supposed to be the same 266
19:11.55beewoolie-afkThere are lots of ways that the systems could be different.  Has anyone looked at the clock pin?
19:12.33[g2]beewoolie-afk, that's what we're asking ep1220  to do :)
19:12.55[g2]If you've got an analyzer handy pls feel empowerered :)
19:12.57beewoolie-afkHeck, I've got a scope.
19:13.21beewoolie-afkI didn't want to do anything today, anyway...
19:14.23jacquesyeah some hard numbers from scopes (as long as they aren't running at 2x normal speed) would be appreciated
19:18.59*** join/#openjtag dyoung (~dyoung@dyoung.nslu2-linux)
19:19.49jacquesmorning dyoung, it's mad scientist day
19:20.53dyoungit is?
19:21.12dyounglike mad scientists are screwing around with my internet connection?
19:22.40jacquesare they?
19:22.44[g2]hey dyoung
19:22.57jacquesI was referring to mad slug experiments in the laboratory
19:23.24dyoungOh.  I googled it.
19:23.36dyoungTheres actually a "talk like a mad scientists day"
19:23.37jacqueswe're trying to find out if it's aliiive or only ½ alive
19:25.23dyoungAh, Ok read the logs.
19:25.29dyoungwell skimmed them.
19:25.50dyoungI have a scope in my Secret Laborabory (tm) too. :-)
19:27.03dyoungnow that i've googled it, I cant want for 7/27, Talk Like A Mad Scientist Day.
19:27.25[g2]jacques, is always early on stuff ;)
19:28.38jacquesdamn I will need to brush up on my mad scientist lingo for that
19:29.31dyoungI cant think of any catchphrases.
19:29.41dyoungother than the one jacques just said.
19:29.51jacquesyeah, that's kinda the classic
19:30.19jacquesand I guess one would use the word "laboratory" a lot
19:30.19dyoungLooks like the Count here is ready to Plug In The Electrodes.
19:31.19jacquesand "1.21 gigawatts!"
19:31.36dyoungDo mad scientists say "Curses!"
19:31.37dyoung?
19:31.37bw-slugstienbwahhahahha
19:32.24dyoungBeing mad implies that you have been shunned by "normal" scientists.  "They all laughed at my theories on why the slug runs at half speed!  I'll show those fools!"
19:32.30jacquesooh and get one of those jacob's ladder thingies
19:32.42jacquesdyoung, yes that's a great one
19:33.46jacqueswas the martian on bugs bunny a mad scientist?
19:33.53jacqueshe kept talking about his space modulator
19:34.02dyoungDid he have a european accent?
19:34.17jacqueshmm no he just sounded like a cartoon
19:35.18dyoungI cant remember if all mad scientists on the TV have had european accents.
19:35.37jacques"If my calculations are correct, when this baby hits eighty-eight miles per hour... you're gonna see some serious shit."
19:35.53bw-slugstienbwahahahahaha
19:36.36dyoungOk fair enough.
19:36.49dyoungI forgot about him.
19:36.50dyoungheh
19:37.07dyoungFlux Capacitor.
19:41.24bw-slugstienSo, not to be pedantic or anything, but do we even know where the clock pin is available?
19:42.02dyoungthe system clock?  SDRAM clock? or PCI CLock?
19:42.16dyoung(not that I have the answer to any of those questions)
19:42.45bw-slugstienI think I can get the SDRAM clock.  Those pins are exposed.
19:43.33dyoungthat would be a good measure because the SDRAM Clock is supposed to be some divosr of the PCI clock.  But I gotta RTFM to verify that
19:44.01bw-slugstienWell, the PCI clock has to be 33MHz.  Unless there is kernel code to change it.  I set it up in the boot loader.
19:46.48[g2]if I had a scope and JTAG, I'd write a tiny assembler program to loop for 100K iterations toggling the a LED / GPIO line at the start and end
19:46.55[g2]and measure it on the scope
19:47.54ep1220I see the PCI clock
19:48.10ep1220the readout says 32.7MHz
19:48.14ep1220so it is 33Mhz
19:48.40ep1220measured on R68, pin closer to the CPU
19:51.04bw-slugstienI'm getting DC from the SDRAM clocks.  
19:52.34bw-slugstien33MHz from R68.
19:53.43bw-slugstienep1220: Where is your resource for finding which CPU pins are available on the PCB?
19:55.30ep1220Actually this is not the PCI clock but the Ext:bus Clock (U2)
19:55.43ep1220bw-slugstien: http://www.nslu2-linux.org/wiki/Info/GPIOConnections
19:56.20ep1220plus the bare pcis in the same wiki.
20:02.09bw-slugstienAccording to the data sheet, the input oscillator is 33MHz.  If the PCI clock is 33MHz I'm confident that the incoming frequency is the same.
20:02.16ep1220Pics are at: http://www.nslu2-linux.org/wiki/Info/PhotosOfTheInternals
20:02.38ep1220bw-slugstien: As I understand: the DS:
20:02.48bw-slugstienSo, if the CPU is performing slowly, I'm not confident that this is a clock speed issue.
20:02.57ep1220the 33MHz is multiplied to 266MHz
20:03.14bw-slugstienRight.  So, it could be the part itself.
20:03.22ep1220then the PCI and the Ext_Clk are divided down
20:03.22dyoungright.  when I read it I determined the only way that it couldnt be 266Mhz was for the master clock to not be 33Mhz.
20:03.31dyoungbut the osc on the bottom is 33Mhz.
20:03.32bw-slugstienThat could be why these slugs are cheap.
20:03.43bw-slugstienThese are the chips that couldn't run at full speed.
20:03.50ep1220There is a multiplicatin factor for the PLL
20:03.56ep1220It is set up at boot-time
20:04.11[g2]from the pull ups on the expansion address bus
20:04.13bw-slugstienI can check it, but it's the same one I use in both the slug and the avilla.
20:04.24bw-slugstienAvilla doesn'thave this problem.
20:04.25ep1220So e.g. a 512MHz chip can be clocekd lower
20:04.40ep1220But for 266Mhz CPU only 1 setting is allowed
20:05.06dyoungMaybe some undocumented internal fuse?
20:05.30[g2]it's in the CP15 iirc or what ever that register is
20:05.39[g2]the one bw-slugstien reads right at startup
20:05.45dyoungor maybe these are SX's (instead of DX)
20:05.56[g2]:)
20:06.02ep1220dyoung: The 33mhz we measure is divided from the 266MHz.
20:06.15ep1220If the PLL were at 133 we would see 16,5
20:06.35bw-slugstien16,5 what?
20:06.39dyoungMhz
20:06.40[g2]bw-slugstien, 16.5 Mhz
20:06.53[g2]bw-slugstien, do you have an avila ?
20:06.56bw-slugstienThat depends on how the chip is designed.
20:07.26bw-slugstienThey could easily have circuitry to set the CPU speed independent of the PCI speed.
20:07.39dyoungAccording to the DS, they are related.
20:07.45bw-slugstienNo avilla.  [g2] has let me to believe that the avilla runs faster.
20:07.51[g2]it does
20:08.05dyounglike twice as fast?
20:08.16[g2]exactly twice as fast
20:08.27dyoungthats good news.
20:08.37[g2]the bogo mips show up a 266 and the drystones are 2x
20:08.45dyoungit verifies we havnt been hallucinating all this time.
20:08.51bw-slugstienWhere are you seeing the PLL discussion?  I'm reading the guide.
20:08.55[g2]Processor       : XScale-IXP42x Family rev 1 (v5b)
20:08.55[g2]BogoMIPS        : 266.24
20:09.35dyoungbw-slugstien, I'm going on memory.  Lemme open up the document and look, I havnt looked for a few months now
20:09.41[g2]VAX MIPS rating =    199.143
20:09.41[g2]real    0m 14.83s
20:09.41[g2]user    0m 14.29s
20:09.58bw-slugstienHey!  That boy's got a VAX on hand.
20:10.00[g2]that's the drystone number with takes 29 sec
20:10.08[g2]and comes in at 99
20:10.17[g2]all for 5M iterations
20:10.27ep1220bw-slugstien: Check page 393 in the Dev Manual
20:10.32[g2]VAX MIPS rating =     99.572
20:10.32[g2]real    0m 29.33s
20:11.00ep1220bw-slugstien: the section on GPIO14 and 15
20:11.19bw-slugstienMy copy isn't that long.
20:11.36[g2]old copy
20:11.38ep1220the manual has Intel Number: 25248005
20:12.04ep1220IXP42X Developer's Manual
20:12.10ep1220March 2005
20:12.11dyoungiirc, there was an addendum also regarding clocks.
20:12.29dyoungbw-slugstien, if you cant find it I can mail it to you.
20:12.29bw-slugstienThat's the one I've been calling the guide...  I was looking for something more definitive.
20:12.36dyoungoh.
20:12.37dyoungok
20:13.07bw-slugstienI see why you think that this would mean that the CPU couldn't operate at that speed.
20:13.24bw-slugstienI believe they could still have an extra divider circuit for the core input.
20:13.39bw-slugstienThe PLL generates 266, but the CPU receives a /2 signal.
20:13.52ep1220Agree, but never read about such a divider.
20:14.12bw-slugstienThe only way to know would be to write code and time a gpio line....as [g2] suggested.
20:14.21bw-slugstienep1220: agreed.  Doesn't mean it isn't there.
20:14.46ep1220If someone writes a GPIO/LED toggle programm i load it into the cache and measure the result
20:14.55bw-slugstienIBM used to sell two card readers.  One was twice as fast as the other.  The only difference was a gear with 1/2 as many teeth.
20:15.23bw-slugstienep1220: Ah, easy enough to do.  What format do you want.
20:16.12ep1220ideally the HEX values I have to put into the cache (as ASCII text)
20:16.40ep1220should be written so it can run right from reset
20:17.00*** join/#openjtag VoodooZ (~VoodooZ@CPE00c0f021712c-CM014110003785.cpe.net.cable.rogers.com)
20:18.52bw-slugstienDo you want the assembler text?
20:18.58[g2]ep1220, our program could be modified do that
20:19.08ep1220bw-slugstien: yes, the assembler text woudl be OK
20:19.35ep1220g2: nod
20:19.49[g2]what's the decrement instruction ?
20:21.01ep1220I think setting the GPIO to 1 and 0 in an endless loop would be best.
20:21.04bw-slugstienadd r0, r0, -1
20:21.15[g2]:)
20:21.22[g2]Ok that's easy
20:21.32bw-slugstienxor on the bit would work.
20:21.32[g2]both the decrement and the toggle
20:22.51ep1220g2: best turn on 1 Led and toggle another
20:23.03ep1220so i can easily see it the prog is loaded correctly
20:23.12[g2]nod
20:24.18[g2]HA
20:24.53[g2]I unplugged the hd so the whole native development environ isn't there anymore :)
20:27.02ep1220[g2]: Toggle D8,9 or 10. Their anode are easy to access.
20:27.34ep1220With D7 some wires are missing on the bare-pics
20:31.18ep1220Sorry, i have to leave now.
20:31.20ep1220g2,bw-slugstien: If You e-mail me the assembly listing I run the test tomorrow morning
20:31.30ep1220good night
20:31.42[g2]sweet dreams
20:31.45[g2]ep1220, THX
20:31.56*** part/#openjtag ep1220 (~NN@gate.epatec.at)
20:32.00bw-slugstiennite
20:34.04bw-slugstienHow about this:
20:34.15bw-slugstienmov r1, #0xc8000000
20:34.15bw-slugstienadd r1, r1, #0x4000
20:34.15bw-slugstienldr r0, [r1, #4]
20:34.15bw-slugstienand r0, r0, #0xfff0
20:34.15bw-slugstienstr r0, [r1,#4]
20:34.16bw-slugstienldr r0, [r1, #0]
20:34.21bw-slugstienand r0, r0, #0xfff0
20:34.29bw-slugstienorr r0, r0, #1
20:34.29bw-slugstien0:str r0, [r1, #0]
20:34.29bw-slugstienxor r0, r0, 0x3
20:34.30bw-slugstienb 0b
20:34.47bw-slugstienI'm trying to be safe, reading the existing contents and setting the bits I care about.
20:38.03[g2]or old code was
20:38.42[g2]<PROTECTED>
20:38.42[g2]<PROTECTED>
20:38.42[g2]<PROTECTED>
20:38.42[g2]<PROTECTED>
20:38.43[g2]<PROTECTED>
20:38.45[g2]<PROTECTED>
20:38.47[g2]<PROTECTED>
20:38.49[g2]<PROTECTED>
20:38.51[g2]loop:
20:38.53[g2]<PROTECTED>
20:38.58[g2]I like the add
20:39.06[g2]save an instruction
20:46.44bw-slugstienI've got one that compiles.
20:46.49bw-slugstien<PROTECTED>
20:46.49bw-slugstien<PROTECTED>
20:46.49bw-slugstien<PROTECTED>
20:46.49bw-slugstien<PROTECTED>
20:46.49bw-slugstien<PROTECTED>
20:46.51bw-slugstien<PROTECTED>
20:46.55bw-slugstien<PROTECTED>
20:46.57bw-slugstien<PROTECTED>
20:46.59bw-slugstien<PROTECTED>
20:47.01bw-slugstien<PROTECTED>
20:47.05bw-slugstien<PROTECTED>
20:47.07bw-slugstienI'll send it in an email.
20:49.01[g2]I think the thing to goggle is either a 0x2 or 0x4 for disk1 or disk2 leds
20:49.18[g2]I'd have to see the traces ep1220 was referring to
20:49.30dyounggoggle?
20:49.30bw-slugstienI am.
20:49.33dyoungGoogle?
20:49.34dyoungToggle?
20:49.46bw-slugstienThe regster is loaded with 0x5 and xor'd with 0xf.
20:50.11bw-slugstienthat will go back and forth between the disk leds.  And it will light the red/green alternatively.
20:50.18[g2]heh goole
20:50.20[g2]google
20:50.25bw-slugstienam I missing something.
20:50.33bw-slugstienboogle.
20:50.46bw-slugstienSending it in email.  Untested, but it compiles.
20:51.10[g2]I guess those are separate lines to the LED and your hitting both
20:51.37[g2]so off / orange / off / orange
20:52.30bw-slugstienRight.
20:52.56[g2]that'll work
20:53.44[g2]did you send that to ep1220 too ?
20:53.58[g2]cool thx
20:55.47dyoungboggle
20:55.49dyoungDongle?
20:55.52dyoungDoggle?
20:56.12[g2]bw-slugstien, that' branh looks a little funny
21:04.42[g2]I've gotta run out for a bit
21:04.43[g2]bbl
21:04.52[g2]THX for all the help
21:38.49*** join/#openjtag ByronT (ByronT@ByronT.nslu2-linux)
23:39.15*** join/#openjtag nslu2-log_ (dyoung@dyoung.nslu2-linux)

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