| 09:10.02 | *** join/#openjtag purl (ibot@apt.bot.TimRiker.active.supporter.pdpc) |
| 09:10.02 | *** topic/#openjtag is This is the place to discuss development of Open JTAG tools and Bootloaders |
| 10:10.39 | *** join/#openjtag [g2] (~g2@g2.nslu2-linux) |
| 11:09.18 | *** join/#openjtag ep1220 (~ep1220@gate.epatec.at) |
| 12:40.44 | ep1220 | [g2]: ? |
| 13:52.23 | [g2] | ep1220, HEY! |
| 13:55.26 | ep1220 | hey |
| 13:55.37 | ep1220 | there is a new problem. |
| 13:55.51 | ep1220 | TRST seems to be actively driven. |
| 13:56.47 | ep1220 | this means R135 likely must be uninstalled |
| 13:57.14 | ep1220 | and a proper driving of this signal during reset must be ensured |
| 13:58.40 | ep1220 | but there are also good news: |
| 13:58.57 | ep1220 | My NSLU2 has a JTAG interface and is still alive :-) |
| 13:59.20 | ep1220 | I got the FTDI in JTAG on channel A and Rs232 on Channel B |
| 13:59.35 | ep1220 | It nicely relays Redboot messages at startup |
| 15:17.34 | [g2] | ep1220-away, CONGRATS! |
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| 18:01.45 | *** join/#openjtag ka6sox (ka6sox@ka6sox.nslu2-linux) |
| 18:02.17 | *** join/#openjtag ep1220 (~ep1220@gate.epatec.at) |
| 18:02.31 | ka6sox | hiya ep1220 |
| 18:02.39 | ep1220 | Hi ka6sox |
| 18:03.17 | ep1220 | did You find time to work on the schematic ? |
| 18:03.48 | ka6sox | ep1220: yes I did...but I have questions. |
| 18:04.12 | ep1220 | I am all ears |
| 18:04.21 | [g2] | ep1220, congrats on the FTDI ! |
| 18:04.31 | ep1220 | [g2] THX! |
| 18:04.35 | ka6sox | I was wondering about the /reset pin and how it is implemented. |
| 18:05.02 | ep1220 | It is an o.C or o.D. |
| 18:05.28 | ka6sox | okay is there a particular pin that it is implemented on? |
| 18:05.38 | ka6sox | (I don't see anything about it in the docs) |
| 18:05.51 | ep1220 | Yuo mean on the JTAG header ? |
| 18:06.23 | ep1220 | Or maybe You mean /reset on the FTDI 2232 ? |
| 18:06.38 | ep1220 | I was talking about XScale Reset |
| 18:07.30 | ka6sox | oh..I was refering to the FTDI chip pin |
| 18:08.16 | ep1220 | I C. the FTDI: reset is generated internally. |
| 18:08.42 | ep1220 | So You can just wire the /reset to Vcc. |
| 18:09.43 | ka6sox | okay the pin out of the FTDI chip to the Xscale is? |
| 18:10.13 | ep1220 | FTDI reset != Xscale Reset. |
| 18:10.25 | ka6sox | (not assuming that there isn't a specific pin that is used for /reset to the Xscale) |
| 18:10.48 | ka6sox | in this case I want the pin that goes to the Target. |
| 18:10.56 | ep1220 | My prototype uses GPIOL1. followed by a MOSFET to make it open-drain. |
| 18:11.10 | ep1220 | You will pass it thru the CPLD I asume. |
| 18:11.28 | ka6sox | yes and then I'll implement OC in the CPLD |
| 18:12.04 | ep1220 | good plan |
| 18:12.42 | ep1220 | Do You still plan to use OC for CPLD->FTDI connection ? |
| 18:12.52 | ka6sox | okay so GPIOL1(FTDI)->CPLD(in)->CPLD(oc)->Xscale(!reset) |
| 18:13.21 | ka6sox | OC is only for the Output connections to the Target. |
| 18:14.14 | ep1220 | XSCALE Reset: yes. But make sure it is OC even when the FTDI is not yet initialized. |
| 18:15.07 | ep1220 | Maybe use GLIOL2 as a general JTAG out enable pin (active low, as it has a pullup) |
| 18:17.38 | ka6sox | okay and the pullup is internal. |
| 18:17.52 | ep1220 | Yes is internal |
| 18:18.03 | ep1220 | I take this back. GPIOL1 has a pullup as well and You can do the OC non-inverting, right ? |
| 18:18.19 | ka6sox | the CPLD can do the inversion. |
| 18:18.35 | ka6sox | to make it right again. |
| 18:19.25 | ka6sox | I was looking to make this dongle have RS232 available so it has all the connections to do debug work. |
| 18:19.38 | ep1220 | good |
| 18:19.53 | ep1220 | I did this today. |
| 18:20.30 | ep1220 | but requires to have proper USB IDs sent by the chip. |
| 18:20.48 | ep1220 | So You need to add an EEPROM. |
| 18:21.06 | ka6sox | I planned on that... |
| 18:22.13 | ep1220 | Let us talk about the OC to the JTAG target. |
| 18:22.31 | ka6sox | k |
| 18:22.42 | ka6sox | back in 5 minutes. |
| 18:22.48 | ep1220 | till then. |
| 18:31.27 | ka6sox | back |
| 18:31.46 | ep1220 | Looked at the datasheets. Think You do not need OC. |
| 18:32.08 | ep1220 | FTDI has VCCIO at 3.3V. Input thershold is max. 1.5V |
| 18:32.28 | ep1220 | Xilinx at 2.5V VCCIO has Vout min 1.9V |
| 18:32.47 | ep1220 | so they should talk toeach other |
| 18:33.05 | ep1220 | Xilinx has n.P. with Inout 3.3V |
| 18:33.15 | ep1220 | s/inout/Input/ |
| 18:33.23 | ka6sox | yeah..I'm not worried about the FTDI<->CPLD connection. |
| 18:33.33 | ka6sox | only the CPLD<->Target connection. |
| 18:34.45 | ep1220 | Don't You use CPLD VCCIo == Target VCC ? |
| 18:35.30 | ka6sox | no because there is only 1 Vccio connection to the CPLD |
| 18:36.02 | ka6sox | so I'm going to use the 5v tolerance of the CPLD for receiving from target and OC for talking to Target |
| 18:36.45 | ep1220 | Isnt the CPLD 3.3V outputvoltage 5V TTL compatible ? |
| 18:37.16 | ep1220 | if this is the case then You do not need OC |
| 18:37.31 | ka6sox | yes but I wanted this device to work on devices with 2.5v I/O as well. |
| 18:37.50 | ka6sox | so using a OC will allow us to use it for 2.5v-5.0v devices. |
| 18:38.34 | ep1220 | You always want the CPLD VCCIO at 3.3V ? |
| 18:38.58 | ka6sox | yes |
| 18:39.12 | ka6sox | so that it properly interfaces to the FS |
| 18:39.17 | ka6sox | er FTDI chip |
| 18:40.06 | ep1220 | As I said above: The FTDI will not have problems seeing the CPLD 2.5V hi-voltage |
| 18:40.20 | ep1220 | and recognizing it as Hi level. |
| 18:40.25 | ka6sox | what about 5.0v? |
| 18:40.59 | ep1220 | the FTDI will never see 5V. it is fixed at 3.3. |
| 18:41.38 | ep1220 | With target at 5, CPLD must have VCCIO 3.3 |
| 18:41.59 | ep1220 | Again no prob CPLD -> FTDI |
| 18:42.01 | ka6sox | it makes it simpler (only 1 Voltage regulator) with the CPLD (3.3v Core) if I just make it 3.3v (core and I/O) |
| 18:42.18 | ep1220 | that is right. |
| 18:42.31 | ep1220 | but OC can limit JTAG speed |
| 18:42.47 | ep1220 | when YOu have a target with many devices in the jain. |
| 18:43.07 | ep1220 | TMS and TCK then might have to drive higher capacitive load. |
| 18:45.02 | ep1220 | One possibility: Take the CPLD VCCIO from the target for 2.5V |
| 18:45.16 | ep1220 | and from internal 3.3 for the other 2. |
| 18:45.29 | ep1220 | Would only require a jumper/switch. |
| 18:45.44 | ka6sox | okay |
| 18:45.54 | ep1220 | And the CPLD can be easily configured to do OC or pull/push. |
| 18:45.56 | ka6sox | you are right about OC limitig speed. |
| 18:47.52 | ep1220 | I suggest You also add a pull-down (10K) to the JTAG TRSTn. |
| 18:48.30 | ep1220 | This makes sure a target can properly reset even if the JTAG-Probe is not activated. |
| 18:49.02 | ep1220 | XSCALE e.g. needs TRSTn low during reset, else the JTAG controller might not initialize. |
| 18:49.45 | ka6sox | okay so things that don't use it are not affected |
| 18:50.33 | ka6sox | do you use Xilinx or Altera? |
| 18:50.39 | ep1220 | yes. Only affects the JTAG controller. |
| 18:51.21 | ep1220 | I used Xilinx and small PLDs (lattice, AMD, ...) |
| 18:51.33 | ep1220 | no experience with ALTERA. |
| 18:51.43 | ka6sox | okay..me too. |
| 18:51.50 | ep1220 | actually Xilinx is also some time back ... |
| 18:52.02 | ka6sox | started with PAL's a bunch of years ago. |
| 18:52.45 | ep1220 | When I started Xilinx did not yet exist :-) |
| 18:57.03 | ep1220 | do You have more questions ? |
| 18:58.05 | ka6sox | no..I'm in Northern California (about 10hrs from home) and will look at the logs when I get home to reference. |
| 18:58.21 | ka6sox | this has been most helpful. |
| 18:58.39 | ep1220 | I am glad I could help. |
| 18:59.10 | ep1220 | BTW: Who is the Xscale bootloader expert in this channel ? |
| 18:59.23 | ka6sox | beewoolie |
| 19:00.01 | ep1220 | Is he here often ? |
| 19:00.11 | ep1220 | Did not yet see this nick. |
| 19:00.47 | ka6sox | yes he has been here often...also [g2] has been doing a lot of work with him. |
| 19:01.19 | [g2] | beewoolie is quite excited about the possibility of loading the i-cache |
| 19:01.39 | ep1220 | I might have some questions for him. |
| 19:02.06 | ka6sox | [g2]: that seems to be the best method of programming the bootloaders fast. |
| 19:02.14 | [g2] | I'm sure we all will have questions :) |
| 19:02.56 | ep1220 | I soon need a small prog to load into the i-cache. |
| 19:03.17 | ep1220 | if I want to look at bootlaoder source: |
| 19:03.26 | ep1220 | would You say redboot is OK ? |
| 19:03.42 | ka6sox | seems complicated. |
| 19:03.59 | ep1220 | is there are simpler one ? |
| 19:04.06 | ka6sox | APEX |
| 19:04.40 | [g2] | http://wiki.buici.com/twiki/bin/view/Main/ApexBootloader#IXP42x_and_the_Linksys_NSLU2_aka |
| 19:05.14 | ep1220 | THX for the link. |
| 19:05.17 | ka6sox | I need to get on the road...long trip ahead. |
| 19:05.19 | [g2] | ep1220, please let us know if you are ready, I've built and run APEX on the NSLU2 |
| 19:05.48 | [g2] | I'll be happy get you an image or help you build you own image that should work |
| 19:05.51 | ep1220 | ka6sox: have a good trip. |
| 19:05.59 | [g2] | safe travels ka6sox |
| 19:06.12 | ep1220 | [g2]: in first step i want something very simple. |
| 19:06.31 | ep1220 | A prog which just turns on an LED :-) |
| 19:06.44 | [g2] | OK. |
| 19:06.57 | ep1220 | most likely the Xscale needs some basic initialization. |
| 19:07.08 | ep1220 | that#s why i want to look at bootloader source |
| 19:07.10 | [g2] | APEX already does the XMAS-tree dance on the LEDs |
| 19:07.27 | ep1220 | How large is it ? |
| 19:09.44 | [g2] | APEX is only 16K |
| 19:09.56 | [g2] | we could fit 2 copies in the icache :) |
| 19:10.24 | ep1220 | there are 2 i-caches. |
| 19:10.49 | ep1220 | the mini-i-cache is 2K (on devices with 32K i-cache) |
| 19:10.58 | ep1220 | Jtag can write to both. |
| 19:11.25 | ep1220 | but only the mini-i-cache can not be invalidated by the CPU |
| 19:11.40 | ep1220 | so it is safer, and usually used for debugging. |
| 19:13.06 | ep1220 | If i start with the full thing, i might have a harder time tracing down problems |
| 19:17.30 | [g2] | ep1220 so you'd like a program for the mini-cache that turns on an LED or toggles an LED ? |
| 19:17.54 | ep1220 | yes. |
| 19:18.26 | ep1220 | Turn on and stay in an endless loop |
| 19:19.00 | ep1220 | best a different LED than used by the original NSLU bootloader. |
| 19:19.27 | [g2] | ok |
| 19:22.03 | ep1220 | may i interpret this: you volunteer to write one ? :-) |
| 19:24.09 | [g2] | I'm wondering if we can write out the serial port |
| 19:25.20 | ep1220 | I know too little about the Xscale peripherals .. |
| 19:25.35 | [g2] | I'll send e-mail to beewoolie |
| 19:25.55 | [g2] | I'm sure either he or I should be able to get you setup |
| 19:26.02 | ep1220 | THX ! |
| 19:26.07 | [g2] | are you ready now ? |
| 19:26.45 | ep1220 | I ahve no more questions. |
| 19:27.25 | [g2] | your serial connection is working at 115200 ? |
| 19:27.34 | ep1220 | yes. |
| 19:27.35 | [g2] | and you are ready to test now |
| 19:28.04 | ep1220 | no. First I have to solve the issue with TRST. |
| 19:28.27 | [g2] | ok.. so you should be ready to test soon |
| 19:28.42 | ep1220 | next 2 days my time is thight. |
| 19:29.01 | ep1220 | should be ready friday/weekend. |
| 19:29.29 | [g2] | okay... I send e-mail to beewoolie now and try to make sure we are ready when you are |
| 19:29.38 | [g2] | possibly with several tests |
| 19:29.43 | [g2] | like LED first, |
| 19:29.47 | [g2] | then serial |
| 19:29.54 | [g2] | then whole thing |
| 19:30.10 | [g2] | or maybe serial + memory controller |
| 19:30.16 | [g2] | and flash |
| 19:30.25 | [g2] | sound like a good plan ? |
| 19:30.29 | ep1220 | would be great, best in this order. |
| 19:30.40 | [g2] | Ok... |
| 19:30.47 | [g2] | I'm off to write some e-mails |
| 19:30.47 | ep1220 | to get me started, just the LED suffices .. |
| 19:31.13 | [g2] | well the whole bootloader is already done, it's just making stuff in a format you can use |
| 19:31.39 | ep1220 | I need to write the Data to the JTAG. |
| 19:32.00 | ep1220 | So best format would be a c file. |
| 19:32.22 | ep1220 | in there an array int bootProg[] = { ... } |
| 19:32.41 | ep1220 | but an object or image would do as well. |
| 19:32.43 | [g2] | ok |
| 19:32.54 | ep1220 | i know how to get the data out there. |
| 19:33.17 | [g2] | it's trivial to convert the object/data to a c structure |
| 19:33.51 | ep1220 | agree. |
| 19:33.59 | [g2] | Ok.. I'll be on it |
| 19:34.29 | ep1220 | THX. for sure safes me a lot of time. |
| 19:34.42 | [g2] | as your work saves us a lot of time |
| 19:34.59 | [g2] | working together we can really move mountains :) |
| 19:36.05 | ep1220 | yes, we can get things done much faster. |
| 19:36.15 | ep1220 | when working together |
| 19:41.34 | [g2] | ep1220, isn't the 2K mini-cache a data cache ? |
| 19:41.52 | ep1220 | there is a mini-data-cache. |
| 19:42.00 | ep1220 | but also a mini i-cache. |
| 19:42.10 | [g2] | ah... |
| 19:42.15 | ep1220 | the mini-i-cache can only be loaded thru JTAG. |
| 19:42.27 | [g2] | really ? |
| 19:42.58 | ep1220 | yes. that's why it is not mentionend in the more general sections of the manual. |
| 19:43.16 | ep1220 | and only few people now about it. |
| 19:43.29 | [g2] | it sounds like this is specifically setup for doing what we are doing |
| 19:43.42 | ep1220 | yes. it is for debugging only. |
| 19:43.54 | [g2] | or board bring up :) |
| 19:44.22 | ep1220 | right. |
| 19:44.26 | [g2] | heh |
| 19:45.39 | ep1220 | Only Intel has this nice feature (AFAIK) |
| 19:45.54 | ep1220 | On ARM and MIPS doing the same thing is a more complicated. |
| 19:46.15 | [g2] | actually, the Cirrus has a buffer that can be loaded via SERIAL |
| 19:46.34 | [g2] | but that needs a hw jumper |
| 19:46.45 | ep1220 | I only know about JTAG debugging ;-) |
| 21:18.28 | Jacmet | the extra blocks could be skipped if we went for a std redboot |
| 21:18.38 | Jacmet | argh |
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