| 00:19.01 | *** join/#openjtag rand (~boole@netblock-66-245-225-188.dslextreme.com) |
| 00:19.50 | ka6sox-away | hi rand! |
| 00:20.01 | rand | hi ka6sox! |
| 00:20.57 | ka6sox-away | Chad has been writing some VHDL and has a VGA test pattern running on his S3 board. |
| 00:23.29 | rand | what's his goal? |
| 00:27.49 | ka6sox-away | dunno...I think to learn VHDL. |
| 00:33.01 | *** join/#openjtag cbpage (~cpage@ip68-6-39-177.sb.sd.cox.net) |
| 00:33.10 | ka6sox-away | Hi there. |
| 00:33.24 | ka6sox-away | what is your goal with the VGA vhdl that your doing? |
| 00:33.47 | cbpage | just playing around really |
| 00:33.56 | cbpage | i got a ball bouncing around pongishly |
| 00:34.04 | rand | fun |
| 00:34.06 | cbpage | going to do more interesting things later... when i get around to em |
| 00:34.34 | cbpage | managed to get an 800x600 mode that works on the lcd |
| 00:34.56 | cbpage | and i have the linux tools installed - including impact |
| 00:35.59 | ka6sox-away | what machine are you doing this on? |
| 00:36.03 | cbpage | spud |
| 00:36.16 | cbpage | i'll have it on my 600e before i go to hawaii... hopefully it'll be somewhat usable ;) |
| 00:37.53 | ka6sox-away | well..for editing and doing impact there won't be a penalty..just synthesis and fit. |
| 00:38.54 | cbpage | yeah |
| 00:39.03 | cbpage | better than nothing ;) |
| 01:30.59 | ka6sox-away | yes indeed...I really like Boo...doing a great job. |
| 02:03.32 | *** join/#openjtag boole2 (~boole@netblock-66-245-225-188.dslextreme.com) |
| 04:06.29 | *** join/#openjtag kas11 (~karen@193-63.73-24.tampabay.res.rr.com) |
| 07:49.47 | *** part/#openjtag kas11 (~karen@193-63.73-24.tampabay.res.rr.com) |
| 18:45.09 | *** join/#openjtag Tiersten (tman@Tiersten.nslu2-linux) |
| 19:01.25 | *** join/#openjtag Tiersten (tman@Tiersten.nslu2-linux) |
| 19:41.12 | *** join/#openjtag kas11 (~kas11@193-63.73-24.tampabay.res.rr.com) |
| 20:56.48 | *** join/#openjtag beewoolie-away (~beewoolie@florence.buici.com) |
| 20:57.32 | beewoolie-away | Any of you folks familiar with the openwince jtag error: chain.c(110) Part 0 without active instruction: |
| 20:57.34 | beewoolie-away | chain.c(110) Part 0 without active instruction |
| 20:58.09 | dyoung | I've never see that one before. |
| 20:58.28 | dyoung | sounds like the one I'm getting with the Xilinx tool |
| 20:58.44 | beewoolie-away | Yeah, I've seen others with the error on one of those parts. |
| 20:59.19 | beewoolie-away | dyoung: do you know where we stand with the openjtag hw? I haven't seen any traffic on it in a while. |
| 21:01.33 | beewoolie-away | I think it means that the BSDL data has not been properly translated. |
| 21:01.42 | beewoolie-away | ...the error |
| 21:13.51 | dyoung | Hmm, looks like it, or its wrong for the part, or the cable is doing something funky. |
| 21:14.17 | dyoung | I dunno the status. The board might be laid out but I'm not sure. |
| 21:24.28 | beewoolie-away | I don't think it's getting as far as checking the manufacturer. |
| 21:24.41 | beewoolie-away | Also, I've read other messages and it doesn't seem to be the cable because other SW works fine. |
| 21:28.23 | dyoung | Hmm |
| 21:28.42 | dyoung | I havnt dove into the bowels of that code yet. |
| 21:28.49 | beewoolie-away | I mean, other people have used different sw with the same cable and target. |
| 21:29.07 | beewoolie-away | Me neither. I'm unimpressed with the fact that they don't read bsdl files directly. |
| 21:29.42 | beewoolie-away | Seems like an obvious design fauxpaw |
| 21:31.07 | beewoolie-away | I was trying to interface my find-and-dandy JTAG board to another device to determine whether or not the board works. |
| 21:31.37 | beewoolie-away | Negative result is, unfortunately, ambiguous. |
| 21:42.07 | *** join/#openjtag Tiersten_ (tman@Tiersten.nslu2-linux) |