07:55:31 | mmatten | hi |
08:10:39 | seletz | morning |
08:29:28 | seletz | morning! |
08:30:09 | seletz | getting even more coffee |
08:35:08 | Sammy | evening seletz :) |
08:54:58 | seletz | erikm: morning |
08:55:43 | erikm | morning |
09:06:40 | BZFlag | erikm: tomw's been hacking on tux memory. he has a tux with 32M on board now. |
09:07:19 | BZFlag | and he ordered a 32M sodimm, so the first known 64M tux is close at hand. |
09:17:53 | erikm | BZFlag: sounds nice |
09:28:29 | BZFlag | we spent quite some time bantering about think about getting the 64M sodimm working before realizing that the sa1100 can only address 64M total. =( |
09:28:59 | erikm | it can address more |
09:29:15 | BZFlag | huh? the ram controller? |
09:29:19 | erikm | I haev a LART with 160MB of memory |
09:29:38 | erikm | it can address 128MB per bank, and there are four banks |
09:29:41 | BZFlag | looks to me like four banks of 11x11 is the max no? |
09:30:13 | | 352 |
09:30:13 | BZFlag | ibot (11 + 11) * 4 * 4 |
09:30:41 | | 67108864 |
09:30:41 | BZFlag | ibot 2 ** (11 + 11) * 4 * 4 |
09:31:00 | BZFlag | so how do you get more ram? |
09:32:16 | BZFlag | thats 2 ^ 22 address lines, * 4 bytes * 4 banks. |
09:35:38 | erikm | heh, you should ask jdb |
09:35:58 | erikm | he designed the LART and also designed the 64MB expansion boards |
09:36:22 | seletz | is the SA1100 ram controller different from the sa1110? |
09:36:36 | erikm | seletz: the only difference is that it only support EDORAM |
09:36:47 | BZFlag | so what does your 160M look like? 64 meg on board and then expansion boards? |
09:36:50 | erikm | seletz: while the SA1110 also supports SDRAM |
09:37:03 | erikm | BZFlag: 32MB on lart + 2x64MB expansion board |
09:37:12 | BZFlag | sa1110 has different bank controls too. |
09:37:27 | BZFlag | what does blob show? |
09:37:47 | | 160 |
09:37:47 | BZFlag | ibot 64 * 2 + 32 |
09:37:57 | erikm | BZFlag: from the top of my head: 4 8MB regions + 2 64MB regions |
09:38:06 | seletz | hmm, then using MDCNFG:DRAC you can specify numer ow rows/cols of ram chips, bank0/1 and bank2/3 |
09:38:32 | erikm | BZFlag: that's 16MB in bank 0 and 1, and 64MB in bank 2 and 3 |
09:38:39 | BZFlag | seletz: yeah, but on the sa1100 one controls 0-3 |
09:39:08 | BZFlag | hmm. you recall the MDCNFG:DRAC settings? |
09:39:30 | seletz | well, i have it in front of me, but the sa1110 ones. |
09:40:12 | seletz | DRAC=110 is 15 row address bits for ex |
09:40:24 | erikm | phone... |
09:41:08 | seletz | BZFlag: so on sa1100 you can only select one type of ram chip for all 0-3 banks, yes? |
09:41:40 | BZFlag | seletz: yes, and there are only 2 bits on DRAC. 9,10,11,12 rows. |
09:42:55 | seletz | ok, then the sa1100 _is_ different from an sa1110. On SA1110 there are 2x3 bits for DRAC |
09:43:36 | BZFlag | right |
09:44:32 | seletz | maybe you could use some CS signals as additional adress bits? |
09:46:59 | BZFlag | that's what I'm including. 4 banks ( 2 CSs) of 32 bit (4 byte) of 11x11 (or 12x10) roww/column == |
09:47:08 | | 67108864 |
09:47:08 | BZFlag | ibot 2 ** (11 + 11) * 4 * 4 |
09:47:32 | BZFlag | so I can't see how to get past 64M |
09:50:19 | seletz | hmmm |
09:50:41 | seletz | if you just download the lart schematics and have a look? |
09:51:04 | seletz | erik said that the lart has an +64MB expansion board |
09:53:05 | BZFlag | can't find schematics for the 64M board, just the main board. |
09:53:27 | seletz | grrr |
09:54:07 | seletz | does'nt the sa1100 provide more CS signals? |
09:58:37 | BZFlag | don't think so. |
10:01:37 | BZFlag | nCS(3:0) |
10:02:16 | seletz | hmmm, that means 4 CS lines, no? |
10:02:30 | BZFlag | hmm. |
10:05:00 | seletz | i think thats the error in your calc: you say 4 banks -> 2CS lines. But you have in fact 4CS lines, which quadruples your address space. |
10:05:50 | BZFlag | hmm.. 4 banks == 4 cs lines from what I'm reading. |
10:06:03 | seletz | well, with 2CS lines you can address 4 banks, 00 01 10 11 |
10:06:53 | seletz | (but i could be completely and totally wrong) |
10:16:14 | seletz | SIGLUNCH |