irclog2html for blob on 2002.04.04

07:55:31mmattenhi
08:10:39seletzmorning
08:29:28seletzmorning!
08:30:09seletzgetting even more coffee
08:35:08Sammyevening seletz :)
08:54:58seletzerikm: morning
08:55:43erikmmorning
09:06:40BZFlagerikm: tomw's been hacking on tux memory. he has a tux with 32M on board now.
09:07:19BZFlagand he ordered a 32M sodimm, so the first known 64M tux is close at hand.
09:17:53erikmBZFlag: sounds nice
09:28:29BZFlagwe spent quite some time bantering about think about getting the 64M sodimm working before realizing that the sa1100 can only address 64M total. =(
09:28:59erikmit can address more
09:29:15BZFlaghuh? the ram controller?
09:29:19erikmI haev a LART with 160MB of memory
09:29:38erikmit can address 128MB per bank, and there are four banks
09:29:41BZFlaglooks to me like four banks of 11x11 is the max no?
09:30:13352
09:30:13BZFlagibot (11 + 11) * 4 * 4
09:30:4167108864
09:30:41BZFlagibot 2 ** (11 + 11) * 4 * 4
09:31:00BZFlagso how do you get more ram?
09:32:16BZFlagthats 2 ^ 22 address lines, * 4 bytes * 4 banks.
09:35:38erikmheh, you should ask jdb
09:35:58erikmhe designed the LART and also designed the 64MB expansion boards
09:36:22seletzis the SA1100 ram controller different from the sa1110?
09:36:36erikmseletz: the only difference is that it only support EDORAM
09:36:47BZFlagso what does your 160M look like? 64 meg on board and then expansion boards?
09:36:50erikmseletz: while the SA1110 also supports SDRAM
09:37:03erikmBZFlag: 32MB on lart + 2x64MB expansion board
09:37:12BZFlagsa1110 has different bank controls too.
09:37:27BZFlagwhat does blob show?
09:37:47160
09:37:47BZFlagibot 64 * 2 + 32
09:37:57erikmBZFlag: from the top of my head: 4 8MB regions + 2 64MB regions
09:38:06seletzhmm, then using MDCNFG:DRAC you can specify numer ow rows/cols of ram chips, bank0/1 and bank2/3
09:38:32erikmBZFlag: that's 16MB in bank 0 and 1, and 64MB in bank 2 and 3
09:38:39BZFlagseletz: yeah, but on the sa1100 one controls 0-3
09:39:08BZFlaghmm. you recall the MDCNFG:DRAC settings?
09:39:30seletzwell, i have it in front of me, but the sa1110 ones.
09:40:12seletzDRAC=110 is 15 row address bits for ex
09:40:24erikmphone...
09:41:08seletzBZFlag: so on sa1100 you can only select one type of ram chip for all 0-3 banks, yes?
09:41:40BZFlagseletz: yes, and there are only 2 bits on DRAC. 9,10,11,12 rows.
09:42:55seletzok, then the sa1100 _is_ different from an sa1110. On SA1110 there are 2x3 bits for DRAC
09:43:36BZFlagright
09:44:32seletzmaybe you could use some CS signals as additional adress bits?
09:46:59BZFlagthat's what I'm including. 4 banks ( 2 CSs) of 32 bit (4 byte) of 11x11 (or 12x10) roww/column ==
09:47:0867108864
09:47:08BZFlagibot 2 ** (11 + 11) * 4 * 4
09:47:32BZFlagso I can't see how to get past 64M
09:50:19seletzhmmm
09:50:41seletzif you just download the lart schematics and have a look?
09:51:04seletzerik said that the lart has an +64MB expansion board
09:53:05BZFlagcan't find schematics for the 64M board, just the main board.
09:53:27seletzgrrr
09:54:07seletzdoes'nt the sa1100 provide more CS signals?
09:58:37BZFlagdon't think so.
10:01:37BZFlagnCS(3:0)
10:02:16seletzhmmm, that means 4 CS lines, no?
10:02:30BZFlaghmm.
10:05:00seletzi think thats the error in your calc: you say 4 banks -> 2CS lines. But you have in fact 4CS lines, which quadruples your address space.
10:05:50BZFlaghmm.. 4 banks == 4 cs lines from what I'm reading.
10:06:03seletzwell, with 2CS lines you can address 4 banks, 00 01 10 11
10:06:53seletz(but i could be completely and totally wrong)
10:16:14seletzSIGLUNCH

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