irclog2html for blob on 2001.09.07

00:17:39sammymorning *
02:35:25sammyConfuse ...
02:42:06sammyAmm.....how to sent kernel into flash ?
02:42:21sammyserial port , or jtag ?
02:42:45sammyGuru ? Russ ?
03:13:10BZFlageither will work.
03:46:00sammyif kernel put into 0xc0800000 what is the 0xc0000000 until 0xc0800000 put ?
06:18:42Russyes sammy?
06:24:13RussI'm here
06:24:58sammysome question but not about blob want to asking you ...
06:25:28sammythe kernel start at 0xc0800000 ,
06:26:59sammyand how is the ram fall into rank......I mean what is in the 0xc0000000
06:27:10sammyuntil 0xc0800000
06:29:14sammyand in 32MB ram , how is that to set ram address ...?
06:31:59sammyand by BZFlag say flash the kernel can use serial port or jtag ? but how did the Jflash know that's the kernel , not the blob or other file , and where is the kernel address in flash memory ?
06:32:56sammysorry ask too much , can you to digest this ?
06:59:00BZFlagthe kernel location in flash is set inside blob. It copies it out to ram before running it.
06:59:27BZFlagnormally you use jtag to flash blob, and then use blob to flash kernel and filesystem.
06:59:38BZFlagblob knows where to put the kernel.
07:00:01BZFlagyou can watch the serial console while blob is booting and it shows where it is copying from.
07:04:25sammythanx Guru...
07:06:55BZFlaggrins
07:22:01Russsammy: the space between 0xc0000000 and the start of the kernel is used for a standard place to put things the kernel needs, like the command line
07:22:40Russif you look at the sa1100 datasheet, you'll see that the first ram bank is at the physicall address 0xc0000000
07:27:49sammybut where is the kernel start at flash memory ?
07:28:04sammyafter the blob ...or
07:28:20Russthe kernel is stored more or less like a file in flash memory
07:28:37Russblob stores it at some location, and then when blob starts, it copies the kernel into ram
07:29:05sammythe image file...(kernel)
07:30:34sammyso we don't need to care where is the kernel " file ", put in where of the flash memory ?
07:31:03Russright
07:31:23Russwe are adding support for loading the kernel from other locations right now (like the network)
07:32:40sammyuse Ethernet ?
07:33:01Russyes
07:34:48sammybut if we don't care we only have 4MB flash memory , how do I know the kernel size won't pass over it ?
07:35:51Russsome #defines in blob tell it where to store the kernel in flash, and how big it can be
07:42:17sammylast question what is the table from 0xc0000000 to 0xd0000000
07:42:24Russ?
07:42:28sammyif I have 32 MB RAM .
07:42:29Russlook in the sa1100 manual
07:42:41Russthe first dram bank is at 0xc0000000
07:42:46Russthe second at 0xc8000000
07:42:55Russthe third at 0xd0000000
07:43:00sammy4 MB or 8MB
07:43:03Russthe fourth at 0xd8000000
07:43:21Russwhat table?
07:43:46sammyfrom 0xc0000000 to 0xc8000000 = 8 MB ?
07:44:03Russpull out your calculator and see
07:45:04sammyand the kernel start in 0xc0800000
07:45:14sammy?
07:45:34Russ0xc8000000 - 0xc0000000 = 0x8000000)
07:45:41Russ0x80000000 = 128MB
07:45:46Russer
07:45:58Russ0x8000000 = 128MB
07:47:05Russa quick look at blob/include/main.c shows:
07:47:13Russ/* where does the kernel live in RAM */
07:47:13Russ#define KERNEL_RAM_BASE      (0xC0008000)
07:47:44sammyso if 32MB RAM , in 0xc0000000 only use 8MB long , and next 8MB start at 0xc0800000 ,  and so .... ?
07:48:00Russwhy would it?
07:49:28sammybecause like you say , the first bank is at 0xc0000000 , second bank at 0xc8000000
07:49:46Russright, so each bank can hold up to 128MB of ram
07:50:07Russit doesn't mean each bank needs to hold 128M of ram
07:50:19Russthats why blob does that alias checking stuff
07:50:39Russits just the same 8M of ram over and over again (16 times)
07:52:10sammyso if the LART define 32MB ...it must be like this...
07:52:32Russit shows the layout in the boot messages of blob
07:52:38Russyou can also see it in the schematic
07:54:29sammy0xc0000000
07:54:30sammy8MB long
07:54:31sammy. <no use>
07:54:32sammy. <no use>
07:54:33sammy. <no use>
07:54:34sammy0xc8000000
07:54:35sammy8MB long
07:54:36sammy. <no use>
07:54:37sammy. <no use>
07:54:38sammy. <no use>
07:54:40sammy0xd0000000
07:54:42sammy8MB long
07:54:44sammy. <no use>
07:54:46sammy. <no use>
07:54:48sammy. <no use>
07:54:49Russnope
07:54:50sammy0xd8000000
07:54:52sammy8MB long
07:54:54sammy. <no use>
07:54:56sammy. <no use>
07:54:58sammy. <no use>
07:54:58Russonly the first two banks are used
07:55:00sammysomething like this right ?
07:55:02sammy? why ?
07:55:12Russwhy? because there are only 4 chips
07:55:35Russone of the address lines is skipped, so I think its something like:
07:55:56Russ0xc0000000: first 8M of first bank (region A)
07:56:03Russshadow of region A
07:56:14Russsecond 8M of first bank (region B)
07:56:22Russshadow of region A
07:56:27Russshadow of region B
07:56:46Russer
07:57:25Russ0xc0000000: A, A, B, B, A, A, B, B, A, A, B, B, A, A, B, B
07:57:36Russthe second bank is the same way:
07:57:50sammyand it must be like this ...........
07:57:53Russ0xc8000000: C, C, D, D, C, C, D, D, C, C, D, D, C, C, D, D
07:58:18sammy0xc0000000
07:58:19sammy8MB long
07:58:20sammy. <no use>
07:58:21sammy. <no use>
07:58:22sammy. <no use>
07:58:23sammy0xc1000000
07:58:24sammy8MB long
07:58:25sammy. <no use>
07:58:26sammy. <no use>
07:58:27sammy. <no use>
07:58:29sammy0xc8000000
07:58:31sammy8MB long
07:58:33sammy. <no use>
07:58:35sammy. <no use>
07:58:37sammy. <no use>
07:58:39sammy0xc9000000
07:58:41sammy8MB long
07:58:43sammy. <no use>
07:58:45sammy. <no use>
07:58:47sammy. <no use>
07:58:49sammycheck again , teacher ,
07:58:51sammyright ?
07:58:57Russno
07:59:15Russthe regions are shadowed over and over again
07:59:27Russso anywhere you look in the first two bank, you find memory
08:00:26sammy........? there is a knife in my head ...#$@%^#$%
08:00:29RussCS majors seem to have trouble with the concept shadow regions and overlapping regions
08:00:50Russok, if it tries to access 0xc4000000
08:01:15Russit will put the address 0x4000000 on the address bus, and select bank 0
08:01:41Russso, A24 is active, all the other address lines are inactive
08:01:55Russbecause its only a 16M chip, A24 isn't connected to anything
08:02:06Russso the chip see address 0x0000000
08:02:16Russand returns the data there
08:02:35Russso reading from location 0xc0000000 and 0xc4000000 give you the same data
08:02:55Russbecause you are just changing A24, which isn't connected to anything
08:03:31Russor is that A26
08:03:38Russyah, A26, sorry
08:04:12Russthe last address lines attached to the chip would be A23, but A24 is connected instead, and A23 isn't connected to anything (you can double check on the schematics)
08:05:12Russso when you access 0xc0000000 and 0xc0800000, you are just toggling A23 (so you are accessing the same location
08:05:35Russits only when A24 becomes active (0xc1000000) that you access the other half of the chip
08:06:03Russthe level of A25 and A26 don't effect the chip
08:07:24Russ(it returns the same data whether or not they are on or off)
08:07:28Russsame case with A23
08:08:47sammyso A23 and A24 map each other  , A25 and A26 map each ohter
08:09:01Russ?
08:09:10Russmap eachother?
08:09:43RussA23, A25, and A26 aren't connected to the DRAM chips at all
08:09:55Russso their values don't matter
08:10:01Russlook at blob/src/memory.c
08:10:06Russand the schematics
08:10:13Russand the sa1100 datasheet
08:11:28sammyok....... starting have a little concept on it
08:11:39Russsleep
08:12:50sammy(((Thanx )))~~~~~~~(long)
08:14:58sammymaybe I should re check out of the source and data sheet...
16:58:05jamey was last seen on #handhelds.org 3 days, 1 hours, 11 minutes and 40 seconds ago, saying: DragonEagle: we have a bunch of safeguards in the load bootldr command: it checks bootldr CRC, architecture, and link address.  It would be fine to do this from Linux with an app that performs similar verification. [Tue Sep  4 16:46:25 2001]
16:58:05Russ|werkibot: seen jamey
21:18:14ed__anyone around
21:18:15ed__la la la la al
21:18:23ed__wakeup!
21:18:46badd00dnoone home.
21:18:54ed__goddamdmit
21:19:01ed__i wanna chew out erik or jd
21:19:01ed__:D
21:20:17Russ|werkjdb and erikm?
21:20:30Russ|werkwhat'd they do?
21:21:21ed__built the lart
21:21:30ed__so my disk keeps saying the cmd times out
21:23:31ed__anyone have disk drive ron there lart
21:23:59Russ|werkI don't know jack about the LART IDE bus, except that its very simple
21:24:25Russ|werkunfortunately, its about midnight where they are, so they are probably gone
21:24:57ed__yeah i know

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