| 00:32:52 | Sammy | hi * |
| 05:32:05 | Sammy | Russ: |
| 05:39:31 | Russ | yes? |
| 05:43:07 | Sammy | why testing chester need to mv to 0x12000000 ? |
| 05:43:23 | Sammy | can I move to other place ? |
| 05:46:14 | Russ | "testing chester"? |
| 05:47:32 | Sammy | oh, in memsetup.s |
| 05:48:30 | Russ | you know thats for the SA-1110, right? |
| 05:49:03 | Sammy | yap. |
| 05:49:30 | Russ | address 0x12000000 is in the SRAM area |
| 05:49:44 | Russ | so you'd need to see the assabet schematics to see what is there |
| 05:49:46 | Sammy | but just confuse .why this place , can be other ? |
| 05:49:53 | Russ | but from the line: |
| 05:49:57 | Russ | mov r2,#0x5000 /* D9_LED on and D8_LED off */ |
| 05:50:14 | Russ | I'm guesing a board control register is there |
| 05:50:37 | Russ | its just turning some led's on and off from what I can tell |
| 05:50:54 | Russ | loads r3 with 0x12000000 |
| 05:51:20 | Russ | leads r2 with 0x5000 (would mean more if you know the bit layout of the board control register) |
| 05:51:40 | Russ | stores r2 at the address r3 (str r2,[r3]) |
| 05:52:34 | Russ | then it does a loop for 0x20000 iterations |
| 05:52:42 | Russ | likely to allow the SDRAM to stabalize |
| 05:52:59 | Russ | any of those parts confuse you? |
| 05:55:40 | Sammy | because from this code and " SA-1110 Development Board Schematics-5.pdf" I can know the thing you say , but only the first "mov r3,#0x12000000" can't image why ? |
| 05:56:39 | Russ | for the instruction "str r2,[r3]", do you understand what that instruction does? |
| 05:57:12 | Sammy | yah ,I know ... |
| 05:57:35 | Russ | what does the instuction do |
| 05:59:14 | Sammy | put the value in r2 into address r3 |
| 06:01:19 | Sammy | da ..da.. ? |
| 06:01:48 | Sammy | wrong ? |
| 06:01:53 | Sammy | yes ? |
| 06:02:33 | Russ | right |
| 06:02:38 | Russ | and what is in r3? |
| 06:02:57 | Sammy | 0x12000000 |
| 06:03:13 | Russ | and what is at address 0x1200000 on the assabet board? |
| 06:03:27 | Russ | er, 0x12000000 |
| 06:04:23 | Sammy | static bank select 2 ? |
| 06:06:34 | Russ | where does CS2 on the board go? |
| 06:10:57 | Sammy | is that SDLC ch1. ? |
| 06:13:15 | Russ | no |
| 06:13:17 | Russ | nCS2 |
| 06:14:13 | Russ | should go along with nCS0, nCS1, ad nCS3 |
| 06:14:19 | Russ | s/ad/and/ |
| 06:16:29 | Sammy | oh oh ,??????? can you show me more detail ? CS2 ,s/ad/and/ ? |
| 06:19:41 | Sammy | thinks .....sorry Russ the foolish student always need the teacher have more patience ... |
| 06:21:10 | Russ | s/ad/and/ is sed for "replace ad with and" |
| 06:21:37 | Russ | so what I said should read "should go along with nCS0, nCS1, and nCS3" |
| 06:21:58 | Russ | if you look at the schematic, nCS0, nCS1, nCS2, and nCS3 should all be togother |
| 06:22:02 | Russ | er, together |
| 06:22:21 | Russ | nCS2 == active low chip select 2 |
| 06:30:40 | Sammy | ok , I fast look that , but what you mean "on the board go " ? |
| 06:33:10 | Russ | there is a pin on the sa-1110 called "nCS2" |
| 06:33:19 | Russ | the schematics show where that signal goes |
| 06:45:21 | Sammy | A little clear now, os that from CPLD to 16_BIT EDGE triggered d-type FF 74LVCH16374A ? right ? |
| 06:45:31 | Sammy | er as |
| 06:46:16 | Sammy | then do on the LED red . right ? |
| 06:47:30 | Sammy | sometimes some detail confuse question like this just around me ... |
| 06:47:46 | Sammy | so I can't look that clear ? |
| 06:48:21 | Russ | if it goes to the CPLD, you'd have to see how the CPLD is setup |
| 06:48:56 | Russ | sleeps |
| 06:49:01 | Sammy | OK ...now is clear |
| 06:49:10 | Sammy | thanx anyway... |